assume in pre-CTS SDC, clock uncertainty for setup contains pll jitter + clock tree skew. How do you set clock uncertainty for hold, and how to modify it to post-CTS sdc?
假设在pre-CTS的时序约束中,setup的clock uncertainty是由PLL jitter和clock tree skew两部分组成,那么
1)pre-CTS的时序约束中,hold的clock uncertainty是什么?
2)post-CTS的时序约束中,setup和hold的clock uncertainty要做什么样的修改?
难度:2