High-speed bus debug and validation test challenges

drjiachen

Abstract
Emerging high-speed bus technologies are presenting new
test challenges for engineering device debug and validation.
These challenges include: Multi-gigabit operating speeds,
multiple-time domains, encoding schemes, non-deterministic
data, DUT-synchronous clocking modes, and SerDes
transceivers with tracking receivers. A key aspect of debug
and validation is the requirement for at-speed functional
testing, requiring high-bandwidth interfacing to maintain
signal integrity at multi-Gbps data rates. Further, these new
communications-like buses require quantification of timing
parameters such as Bit Error Rate, eye opening, and jitter.
Conventional test methods may no longer yield meaningful
results or even be applicable.
As high-speed bus technologies proliferate, they are
expected to replace traditional parallel bus interfaces. New
features and architectural changes are integral to engineering
tester solutions for evaluating devices that use high-speed bus
technologies. This paper introduces an advanced pattern
architecture concept that incorporates sophisticated memory
management optimized for data collection and for
applications such as optical probing and DFT-based
operations. New high-speed bus test challenges and potential
solutions, pertaining to engineering debug and validation test,
are also addressed.

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luan12345678

非常感谢

twdgl

有中文版没

tempxyz

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wjh123

Thanks

fwutsairlin

thank for your sharing

trash_net

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