Testing SoC interconnects for signal integrity using boundary scan

drjiachen

ABSTRACT
As the technology is shrinking toward 50 nm and the working frequency
is going into multi gigahertz range, the effect of interconnects
on functionality and performance of system-on-chips is becoming
dominant. More specifically, distortion (integrity loss) of signals
traveling on high-speed interconnects can no longer be ignored. In
this paper, we extend the conventional boundary scan architecture
to allow testing signal integrity in SoC interconnects. Our extended
JTAG architecture collects and outputs the integrity loss information
using the enhanced observation cells. The architecture fully complies
with the JTAG standard and can be adopted by any SoC that is IEEE
1149.1 compliant. We also propose a simple yet efficient compression
scheme that can be employed by an ATE to minimize the scan-in
delivery time.

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2011-5-21 02:24 上传

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gp7626660

不错，不错

cadance

thanks for sharing

Evgen

thanks

flow2000a

下载 看看