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[招聘] 【招聘】LSI上海研发中心热招ASIC Customer Engineer!!!

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发表于 2011-5-13 14:09:37 | 显示全部楼层 |阅读模式

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LSI上海研发中心正在扩张,目前DI team有很多职业发展机会,欢迎您的加入![url=mailto:可将简历发至tracey.zheng@lsi.com]可将简历发至tracey.zheng@lsi.com[/url]

也可以通过以下方式联系msn: zql975504@hotmail.com/021-24191709

ASIC Customer Engineer

Shanghai Design Center

Education: BS/MS in Electrical, Electronics, or Computer Engineering or Equivalent

Requirements/Qualification:

The candidate should be familiar with one of the following four functional areas:

1) RTL Analysis/Synthesis/STA: The candidate should have strong skills for the front-end of design

implementation which includes RTL analysis, RTL coding guidelines, synthesis strategies, and STA setup

for complex ASIC environment. The candidate should also be familiar with power management at RTL level.

2) Physical Design Implementation: The candidate should be strong in physical design which includes

design planning, floor planning, power planning, placement, CTS, routing, custom routing, parasitic

extraction, STA and hand fix ECO, and other aspects of design closure. Strong Synopsys ICC/Astro

experience is preferred. Strong tcl skill is required. Mentor Calibre DRC and LVS skills are preferred.

3) DFT: The candidate should be strong in all DFT aspects, including scan/TDF, TestKompress,

MEMBIST/BISR, and JTAG. The candidate must have knowledge and hands-on experience with test

insertion, vector generation, and verification. Strong STA skill is preferred for test timing. Experience in

working with test engineering and debugging prototypes is considered a strong plus. Experience with

Mentor/LogicVision and Virage tools is preferred.

4) Physical Verification: The candidate should have sound working knowledge of Calibre (Mentor Graphics)

and have run DRC and LVS on multiple designs at 65nm and 40nm nodes. Should be able to understand

requirements of different DRC and DFM rules and perform fixes in layout efficiently. Being able to analyze

and fix power/ground shorts. Must have a good understanding about LVS and should be able analyze and

fix LVS errors on designs up to 50M gates. Ability to write custom rule sets in Calibre to automate DRC/DFM

tasks will be very valuable. Experience in power analysis with Apache tools is highly preferred.

Job Description:

The ASIC Customer Engineer is a challenging and cutting-edge position working with LSI internal methodology and

IP development teams to support complex state-of-the-art ASIC designs for either external tier one customers or

internal standard product programs. As an integral member of the customer design engineering team, an ASIC

Customer Engineer has responsibility for a wide range of tasks in one or more of the functional areas (RTL/STA,

physical design, DFT and physical verification). Over time, all ASIC customer engineers within the design center are

expected to expand and develop the skills to be able to do most of the tasks covering multiple functional areas.

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