single cycle MIPS CPU with Verilog

eagleice · 发表于 2011-4-27 19:44:49

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This project aims to implement a single cycle MIPS CPU with Verilog. For the beginning, the supported instructions would be:

add,
sub,
and,
or, slt
addi, andi, ori
lw, sw
beq

Hardware Specs:

Register File：32 × 32-bit Registers
Instruction Memory：1KB (256 × 32-bit )
Data Memory：32 Bytes (Memories are modeled in Verilog simply as an array of registers, so we did not care about the memory latency delay)
Address space: Text segment and data segment both begin at address 0x0000 for convenience, different from the real MIPS machine

code

single-cycle-mips-cpu-with-testbench.rar (7.29 KB , 下载次数: 179 )

notfackerd · 发表于 2011-4-27 20:52:01

非常感谢

aimar327 · 发表于 2011-4-27 21:00:25

自己写的？下来学习学习

ultrajet · 发表于 2011-12-20 19:01:36

感謝分享資源

陳郁吟 · 发表于 2014-1-14 23:38:00

回复 1# eagleice

cool!
thank for sharingi think it's really difficult to design cpu

z9886607 · 发表于 2015-4-29 22:31:25

感謝樓主分享

夕阳路人 · 发表于 2015-7-29 15:58:06

回复 1# eagleice

非常感谢！正在学习这个

besarkecil · 发表于 2017-10-7 23:51:54

回复 1# eagleice

thanks

QQben · 发表于 2017-10-8 10:10:41

xxfff

huatiantian · 发表于 2018-5-12 21:50:09

good thx

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[资料] single cycle MIPS CPU with Verilog