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Abstract
The ever-increasing complexity and operating frequencies in state-of-the-art digital systems present the need for more accurate and faster, simulation and modeling techniques. Signal integrity and power integrity analyses in such systems require large-sized system level simulations. Such simulations need considerable resources in terms of CPU memory and simulation time. Hence modeling methodologies are required to perform these simulations efficiently. This paper described several macro-modeling techniques that have been developed to address signal and power integrity issues. Using these techniques transistor level driver and receiver circuits, power distribution networks, and interconnect networks can be efficiently incorporated in system level simulations.
Modeling of Interconnects, Drivers and Receivers in Packaged Systems[Swaminthan].pdf
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