Dissertation: High Performance Continuous-Time Filter

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HIGH PERFORMANCE CONTINUOUS-TIME FILTERS FOR INFORMATION TRANSFER SYSTEMS
A Dissertation
by
AHMED NADER MOHIELDIN
Submitted to the Office of Graduate Studies of
Texas A&M University
in partial fulfillment of the requirements for the degree of
DOCTOR OF PHILOSOPHY
August 2003
Major Subject: Electrical Engineering


TABLE OF CONTENTS
Page
ABSTRACT……………………………………………………………………………. iii
DEDICATION………………………………………………………………………...… v
ACKNOWLEDGEMENTS…………………………………………………………..… vi
TABLE OF CONTENTS…………………………………………………………...… viii
LIST OF FIGURES………………………………………………………………….… xii
LIST OF TABLES…………………………………………………………………...… xx
CHAPTER
I INTRODUCTION…………………………………………………………...…1
1.1. Motivation and Background .................................................................. 1
1.2. Passive Filters ........................................................................................ 5
1.2.1 RLC Filters .................................................................................... 5
1.2.2 Acoustic Filters.............................................................................. 5
1.3. Active Filters ......................................................................................... 8
1.3.1 Active-RC Filters........................................................................... 9
1.3.2 OTA-C Filters.............................................................................. 10
1.3.3 Q-enhanced LC Filters................................................................. 11
1.4. The Approximation Problem............................................................... 11
1.5. High Order Filters................................................................................ 12
1.5.1 Cascade........................................................................................ 13
1.5.2 Multiple-Loop Feedback ............................................................. 13
1.5.2.1 Leapfrog Topology............................................................. 13
1.5.2.2 Summed-Feedback Topology............................................. 14
1.5.3 LC Ladder Simulation ................................................................. 15
1.6. Automatic Tuning Schemes................................................................. 16
1.7. Design Considerations ......................................................................... 21
1.8. Organization ........................................................................................ 22
II A LOW-VOLTAGE FULLY BALANCED OTA WITH
COMMON-MODE FEEDFORWARD AND INHERENT
COMMON-MODE FEEDBACK DETECTOR…………………………….... 27
2.1. Motivation and Background ................................................................ 27
ix
CHAPTER Page
2.1.1 Linearization Techniques............................................................. 29
2.1.1.1 Source Degeneration........................................................... 29
2.1.1.2 Attenuation ......................................................................... 30
2.1.2 CMFB Design Considerations..................................................... 33
2.2. Proposed OTA Architecture ................................................................ 37
2.2.1 Inherent Common-Mode Detection............................................. 41
2.2.2 Inherent Common-Mode Feedforward........................................ 42
2.2.3 CMFB and CMFF Arrangements ................................................ 43
2.2.4 Frequency Response and Excess Phase....................................... 45
2.2.5 Noise Performance....................................................................... 46
2.3. Nonlinearity Analysis .......................................................................... 47
2.3.1 Transistor Mismatches................................................................. 48
2.3.2 Cross Product of Differential and Common-Mode
Input Signals ............................................................................... 49
2.3.3 Short Channel Effects .................................................................. 50
2.3.4 Nonlinear Interaction of Differential OTA Output Signals
AND CMFB ................................................................................ 53
2.4. CMFB Loop Design Considerations ................................................... 61
2.4.1 Common-Mode Loop and Stability Conditions .......................... 61
2.4.2 Common-Mode Gain................................................................... 63
2.5. Linear Phase Filter............................................................................... 67
2.6. Measurement Results........................................................................... 70
2.7. Conclusions ......................................................................................... 78
III A DUAL-MODE LOW-PASS FILTER FOR BLUETOOTH AND
IEEE 802.11B………………………………………………………………... 79
3.1. Motivation and Background ................................................................ 79
3.2. Filter Specifications ............................................................................. 81
3.3. Filter Architecture................................................................................ 86
3.4. Design Trade-Offs ............................................................................... 88
3.4.1 Linearity Analysis........................................................................ 88
3.4.2 Effect of the Single Passive Pole................................................. 90
3.4.3 Noise Analysis ............................................................................. 92
3.4.4 Input Impedance .......................................................................... 93
3.4.5 Output Impedance........................................................................ 94
3.4.6 Design Procedure......................................................................... 95
3.5. OTA Architecture ................................................................................ 96
3.6. Common-Mode Feedback ................................................................... 98
3.7. Simulation Results............................................................................... 99
3.8. Frequency Tuning Scheme ................................................................ 105
x
CHAPTER Page
IV A 2.7V, 1.8GHZ, 4TH ORDER TUNABLE LC BANDPASS FILTER
BASED ON EMULATION OF MAGNETICALLY-COUPLED
RESONATORS………………………………………………………...…... 112
4.1. Motivation and Background .............................................................. 112
4.1.1 On-Chip Inductors ..................................................................... 112
4.1.2 High Order Filters...................................................................... 115
4.2. Q-Enhancement Approach................................................................. 119
4.3. Filter Architecture.............................................................................. 121
4.3.1 Effects of Non-Ideal Inductors .................................................. 122
4.3.2 Effect of Mismatches................................................................. 124
4.3.3 Design Equations ....................................................................... 129
4.3.4 Circuit Implementation.............................................................. 130
4.4. Design Considerations ....................................................................... 132
4.4.1 Power Consumption .................................................................. 132
4.4.2 Noise Analysis ........................................................................... 133
4.4.3 Nonlinearity Analysis ................................................................ 137
4.4.4 Dynamic Range ......................................................................... 139
4.4.5 Design Procedure....................................................................... 141
4.5. Filter Tuning Remarks....................................................................... 141
4.6. Measurement Results......................................................................... 143
4.7. Conclusions ....................................................................................... 149
V A 100MHZ, 8MW ROM-LESS QUADRATURE DIRECT DIGITAL
FREQUENCY SYNTHESIZER………………………………………….... 151
5.1. Motivation and Background .............................................................. 151
5.2. Proposed DDFS Architecture ............................................................ 155
5.3. Linear DAC ....................................................................................... 162
5.4. Switched Weighted-Sum Block......................................................... 164
5.5. Measurement Results......................................................................... 173
5.6. Particular Case................................................................................... 180
5.7. Conclusions ....................................................................................... 182
VI A 2V 11 BITS INCREMENTAL A/D CONVERTER USING
FLOATING GATE TECHNIQUE……………………………………….… 184
6.1. Motivation and Background .............................................................. 184
6.2. Incremental A/D Converter Architecture and Operation................... 188
6.3. Design Considerations ....................................................................... 192
6.3.1 Noise.......................................................................................... 193
6.3.2 Effect of Finite DC Gain............................................................ 193
6.3.3 Effect of Finite GBW ................................................................ 196
xi
CHAPTER Page
6.3.4 Effect of Finite Switch Resistance............................................. 196
6.3.5 Effect of Finite Slew Rate.......................................................... 197
6.4. Block Design ..................................................................................... 197
6.4.1 Operational Amplifier (OpAmp) ............................................... 197
6.4.2 Comparator ................................................................................ 201
6.4.3 CMFB Circuit ............................................................................ 202
6.5. Measurement Results......................................................................... 204
6.6. Conclusions ....................................................................................... 206
VII CONCLUSIONS…………………………………………………………… 208
REFERENCES……………………………………………………………………..… 210
APPENDIX A………………………………………………………………………… 218
APPENDIX B………………………………………………………………………… 231
VITA………………………………………………………………………………….. 233

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