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ARM1176 IEM Low-Power Guide 2009
Foreword
Preface
Acknowledgements
References and Bibliography
Low-Power Links
Power Forward Initiative
Cadence Low-Power Links
CPF Terminology Glossary
Design Objects
CPF Objects
Special Library Cells for Power Management
Introduction to Low Power
Low Power Today
Power Management
Complete Low-Power RTL-to-GDSII Flow Using CPF
A Holistic Approach to Low-Power Intent
Verification of Low-Power Intent with CPF
Power Intent Validation
Low-Power Verification
CPF Verification Summary
Front-End Design with CPF
Architectural Exploration
Synthesis Low-Power Optimization
Automated Power Reduction in Synthesis
CPF-Powered Reduction in Synthesis
Simulation for Power Estimation
CPF Synthesis Summary
Power-Aware Design for Test (DFT)
Power Domain-Aware DFT
Power-Aware Test
CPF Test Summary
Low-Power Implementation with CPF
Introduction to Low-Power Implementation
Gate-Level Optimization in Power-Aware Physical Synthesis
Clock Gating in Power-Aware Physical Synthesis
Multi-Vth Optimization in Power-Aware Physical Synthesis
Multiple Supply Voltage (MSV) in Power-Aware Physical Synthesis
Power Shut-Off (PSO) in Power-Aware Physical Synthesis
Dynamic Voltage/Frequency Scaling (DVFS) Implementation
Substrate Biasing Implementation
Diffusion Biasing
CPF Implementation Summary
ARC Energy PRO: Technology for Active Power Management
Overview of ARC Energy PRO
The Power Struggle
Designing Low-Power Solutions
Project Subsystem: ARC CPU with Co-Processor
Conclusion
NEC Electronics: Integrating Power Awareness in SoC Design with CPF
NEC Electronics and CPF
Why Low Power?
Comprehensive Approach to Low Power
Example of Mobile Phone System SoC
NEC Electronics CPF Proof-Point Project: NEC-PPP
Summary
Fujitsu: CPF in the Low-Power Design Reference Flow
Fujitsu and CPF
Low-Power Design Techniques Used by Fujitsu
Low-Power Test Chip Developed with CPF
Low-Power Design Flow with CPF
Review of Low-Power Test Chip Design
Fujitsu Reference Design Flow 3.0: Low Power with CPF
Fujitsu's CPF Low-Power RDF Methodology
Summary
NXP User Experience: Complex SoC Implementation with CPF
Low Power is Critical to NXP
CPF in Action on a Complex SoC Platform
Power Network Intent
Hierarchical Support for IP and Design Reuse
Scalable Implementation
DFT Impact
CPF-Based Results
Freescale: Wireless Low-Power Design and Verification with CPF
Business Implications of Power
Wireless Carriers and Power
Phone Power and Energy
Active Power Challenge and Design Techniques
Low-Power Design Methodology and CPF
Mobile Application Power Reduction Results
Summary
TSMC: Advanced Design for Low Power at 65nm and Below
TSMC 65nm Low-Power Process
Low-Power Design Techniques
CPF: The Low-Power Standard
The TSMC Proof-Point Project
CPF-Based TSMC Reference Flow 9.0.
TSMC Low-Power Library: CPF Compliant
Summary
ARM: 1176 IEM Reference Methodology
Introduction
ARM-Cadence Implementation Reference Methodologies
ARM1176 Processor
ARM1176JZF-S Low-Power Reference Methodology
Conclusion
Faraday: CPF-Based Low-Power Design Methodology for Platform-Based SoCs
Faraday Design Services and Low-Power Design
Introduction
Faraday CPF Flow
Faraday So Compiler CPF-Enabled Platform-Based Design for Low-Power
A Low-Power Platform-Based Design Example
Faraday CPF Low-Power SoCompiler Design Methodology Summary
Sequence Design: Early Power Analysis with CPF
Design for Power
Nano CPU Design Overview
Conclusions
ARM Cortex iRM: CPF-Driven Low-Power Functionality in a High-Performance Design Flow
ARM and Cadence Collaboration
iRM Flow Setups: Adding Low-Power Functionality to a High-Performance Design Flow
Other Low-Power Functionality Additions to a High-Performance Design Flow
Conclusions and Availability of ARM/Cadence iRMs
When Do You Know You Have Saved Enough Power?
Impact of Low-Power Design
Power Dissipation
Static Power Optimization
Static Power Optimization
Dynamic Power Optimization
ARM Intelligent Energy Manager™(IEM)
Power Savings in Multicore Processors
Conclusions
AMD: Power Gating in a High-Performance GPU
AMD and Low Power
Front-End Low-Power Logical Design/Verification Flow and Methodology
Back-End Low-Power Physical Design/Verification Flow and Methodology
CPF and Results
Summary of Results
ARM 1176-JZFS CPU-Based Low-Power Subsystem:
Methodology to Reduce Electrical and Functional Failure in a Low-Power Design
Abstract
Overview of Ulterior Project
Ulterior Implementation
Assembly and Packaging
Ulterior Implementation Results
Sonics: CPF Flow for Highly-Configurable On-Chip Network IP
Overview
Sonic Power Management Features
CPF Generation and Automation
Sample SoC Design
Sonics CPF-based Low-Power Flow
Low-Power Reference Flow and Tools
Conclusion
Virage Logic: Minimizing Design Complexity with Power-Optimized Physical IP
Virage Logic IP Portfolio
Economics of Battery Life
Economics of IC Cooling
Low Power Design Solutions
Virage Logic Power-Optimization Kit: Standard Cell Set
Standard Cell in the Power Optimization Kit
Using Library CPF for Level Shifters, Retention Flops and Power Switches
40nm SiWare Memory Performance/Power Tradeoffs for Bank and Column Mux
Summary |
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