Circuits and Systems I: Regular Papers 2011 Apr

sun-moon

Analog IC Design in Ultra-Thin Oxide CMOS Technologies With Significant Direct Tunneling-Induced Gate Current
Bohannon, E.  Washburn, C.  Mukund, P. R.  
Page(s): 645 - 653

On the Noise Optimization of CMOS Common-Source Low-Noise Amplifiers
Deng, Z.  Niknejad, A. M.  
Page(s): 654 - 667

Analysis of  Asymmetry in MOSFET Small-Signal Amplifiers
Kim, N.  Aparin, V.  Larson, L. E.  
Page(s): 668 - 676

A Phase and Amplitude Tunable Quadrature  Oscillator: Analysis and Design
GHonoodi, H.  Naimi, H. M.  
Page(s): 677 - 689

Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators
Lee, S.-C.  Chiu, Y.  
Page(s): 690 - 698

A CMOS Instrumentation Amplifier With 90-dB CMRR at 2-MHz Using Capacitive Neutralization: Analysis, Design Considerations, and Implementation
Worapishet, A.  Demosthenous, A.  Liu, X.  
Page(s): 699 - 710

Energy-Saving Cooperative Spectrum Sensing Processor for Cognitive Radio System
Chien, W.-B.  Yang, C.-K.  Huang, Y.-H.  
Page(s): 711 - 723

Dynamical Properties and Design Analysis for Nonvolatile Memristor Memories
Ho, Y.  Huang, G. M.  Li, P.  
Page(s): 724 - 736

Two-Dimensional Partially Differential Cepstrum and Its Applications on Filter Stabilization and Phase Unwrapping
Pei, S.-C.  Lin, H.-S.  
Page(s): 737 - 745

Design of 2-D Wideband Circularly Symmetric FIR Filters by Multiplierless High-Order Transformation
Liu, J.-C.  Tai, Y.-L.  
Page(s): 746 - 754

Multidimensional DFT IP Generator for FPGA Platforms
Yu, C.-L.  Irick, K.  Chakrabarti, C.  Narayanan, V.  
Page(s): 755 - 764

Observations Concerning the Locking Range in a Complementary Differential  Injection-Locked Frequency Divider—Part II: Design Methodology
Daneshgar, S.  De Feo, O.  Kennedy, M. P.  
Page(s): 765 - 776

A 32  32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput
Camunas-Mesa, L.  Acosta-Jimenez, A.  Zamarreno-Ramos, C.  Serrano-Gotarredona, T.  Linares-Barranco, B.  
Page(s): 777 - 790

An Asynchronous Spike Event Coding Scheme for Programmable Analog Arrays
Gouveia, L. C.  Koickal, T. J.  Hamilton, A.  
Page(s): 791 - 799

Adaptive Unknown-Input Observers-Based Synchronization of Chaotic Systems for Telecommunication
Dimassi, H.  Loria, A.  
Page(s): 800 - 812

Lattice Reduction for MIMO Detection: From Theoretical Analysis to Hardware Realization
Gestner, B.  Zhang, W.  Ma, X.  Anderson, D. V.  
Page(s): 813 - 826

Multicarrier Faster-Than-Nyquist Transceivers: Hardware Architecture and Performance Analysis
Dasalukunte, D.  Rusek, F.  Owall, V.  
Page(s): 827 - 838

A High-Throughput LDPC Decoder Architecture With Rate Compatibility
Zhang, K.  Huang, X.  Wang, Z.  
Page(s): 839 - 847

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