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发表于 2011-3-21 23:01:21
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显示全部楼层
module cnt7
(
input clk,
input rst,
input [2:0] data_in,
input load_en,
output reg [2:0] data_out
);
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
data_out <= 3'd0;
else if (load_en == 1'b1)
data_out <= data_in;
else if (data_out >= 3'd6)
data_out <= 3'd0;
else
data_out <= data_out + 3'd1;
end
endmodule |
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