CMOS AUTO-RANGING PLL INTEGRATED CIRCUITS FOR FREQUENCY SYNTHESIZERS

angelweishan

CMOS AUTO-RANGING PHASE-LOCKED LOOP INTEGRATED CIRCUITS FOR
FREQUENCY SYNTHESIZERS AND CLOCK RECOVERY CIRCUITS
by
Yi-Cheng Chang

TABLE OF CONTENTS
LIST OF TABLES ........................................................................................................... viii
LIST OF FIGURES ........................................................................................................... ix
CHAPTER 1 INTRODUCTION ........................................................................................ 1

CHAPTER 2 BASIC CONCEPTS OF PHASE-LOCKED LOOP CIRCUITS ................. 6
2.1. Design of an Analog Phase-Locked Loop ................................................................... 6
2.2. Design ofa Digital (Charge-Pump) Phase-Locked Loop .......................................... 15

CHAPTER 3 BUILDING BLOCKS FOR PLLS ............................................................. 20
3.1. The Typical PLL Circuit. ........................................................................................... 20
3.2. Current-Controlled OscillatorNoltage-Controlled Oscillator (CCONCO) .............. 21
3.2.1. Tuned oscillators ..................................................................................................... 21
3.2.2. Relaxation oscillat .............................................................................................. 23
3.2.3. Ring oscillators .................................................................................................. 24
3.3. D flip-flops and frequency dividers ........................................................................... 28
3.3.1. ECL type D flip-flops ........................................................................................ 28
3.3.2. Dynamic D flip-flops, and T flip-flops .............................................................. 32
3.4. Phase/frequency detectors .......................................................................................... 33
3.4.1. Tri-state phase-frequency detectors ................................................................... 34
3.4.2. Hogge's Phase detectors for clock recovery circuits ......................................... 36
3.5. Rotational frequency detector .......................................................................... , ......... 37
3.6. Differential charge-pump and the second order low-pass filter ................................. 41
3.7. Signal control circuit of the CCO .............................................................................. 42
3.8. Design of the PLL IC layout. ..................................................................................... 44

CHAPTER 4 HISTORICAL REVIEW OF AUTO-RANGING PLLS ............................ 46
4.1. Prior auto-ranging frequency synthesizer by Basset ................................................. 46
4.2. Prior Auto-ranging PLL circuit by Worden .............................................................. 50
4.3. Prior auto-ranging clock recovery circuit by Baumert ............................................. 53
4.4. Prior auto-ranging clock recovery circuit by Park .................................................... 55

CHAPTER 5 DESIGN OF AUTO-RANGING PLL FREQUENCY SYNTHESIZERS 59
5.1. Circuit Design ............................................................................................................ 64
5.1.1. Signal control circuit of the CCO .................................................................... 65
5.1.2. Coarse-steering frequency comparators ............................................................ 68
5.1.2.1. Approach using full-adders ............................................................................ 68
5.1.2.2. Approach using an UP/DOWN counter ......................................................... 71
5.2. Simulation Results ..................................................................................................... 75
5.3. Consideration of the IC layout.. ................................................................................. 81
5.4.. Compa'ns ons to pn.o r art .............................................. ............................... ..... ....... ... 8_/

CHAPTER 6 DESIGN OF THE AUTO-RANGING PLL FOR CLOCK RECOVERY
CIRCUITS ........................................................................................................................ 88
6.1. Bit-rate estimators and pulse-width comparators ...................................................... 90
6.1.1. Proposed bit-rate estimator ................................................................................ 94
6.1.2. Proposed pulse-width comparators .................................................................. 103
6.2. Range-selecting circuit ............................................................................................. 107
6.3. Simulation for the overall auto-ranging CRC .......................................................... III

CHAPTER 7 IC FABRICATION AND TESTING ....................................................... 113
7.1.Single-loop PLL IC ................................................................................................... 113
7. 1.1 . Open-loop oscillator testing setup ................................................................... 114
7.1.2. Closed-loop PLL circuit testing ....................................................................... 116
7.1.3. Single-loop PLL chip micrograph ................................................................... 123
7.2. Auto-ranging PLL IC ............................................................................................... 123
7. _., . 1. T·I me da mai. n c h·I p testi.n g ................................................................................ 1'_J )-
7.2.2. PLL output spectrum testing ........................................................................... 130
7.2.3. Power consumption of the auto-ranging PLL circuit ...................................... 133
7.2.4. Chip micrograph for the auto-ranging PLL IC ............................................... 134
7.3. Summary of the experimental results ..................................................................... 135

CHAPTER 8 CONCLUSIONS ..................................................................................... 136
REFERENCES ............................................................................................................... 138
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