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Position: Senior SerDes Analog IC Design Engineer
Location: Shanghai, China
Position Description
Responsible for the design and development of SerDes analog/mixed signal IC circuit blocks from initial concept and specification through final verification and conformance to customer requirements.
Position Requirements
• Bachelor or master degree in Electronics Engineering and related majors, PHD is preferred.
• Minimum 5 years industry experience in CMOS SerDes IC design
• Experience in SerDes transceiver designs including some of the following circuit blocks: System level modeling by matlab, C, or VerilogA; Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; Bias and Bandgap and Voltage Regulators.
• Good knowledge of a set of common SerDes standards and their electrical requirements, and a thorough understanding of jitter.
• Proficient in using CAD tools for circuit simulation, layout, and physical verification (Cadence tool experience, lab test experience, and experience at 65nm and below technologies are a plus).
• Good in problem solving and communication.
• Ability to work cooperatively in team environment.
MSN: morningjeffdight@hotmail.com |
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