在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 2506|回复: 0

[招聘] Verification Engineer-上海

[复制链接]
发表于 2011-3-3 13:55:30 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x

Verification Engineer

Job Responsibilities:


Reporting to Verification manager, the candidate is expected to be responsible for following tasks:

1.
Apply specialist skills and knowledge in both hardware and software to perform Pre-Silicon verification tasks for complex 40nm Media Processor SOC devices

2.
Perform co-verification of processor models and RTL including application software and firmware verification

3.
Support the development of multi abstraction/views to enable a thorough Soc verification from unit level to system level

4.
Participation in the continued development of verification strategies; evaluate and integrate cutting edge verification/emulation methodologies into the tool flow

5.
Work with other cross functional teams in China and oversea to specify, verify and improve SoC quality and timeliness to production


Job Requirements:

1.
Proficient and experienced with the C/C++ program.

2.
Bachelor degree in Electrical Engineering or related area, MSEE is preferred.

3.
3 years or above experience in ASIC/complex SoC verification. Some RTL design/modeling experience is a plus.

4.
Experience of SOC designs with embedded processor cores and their integration with other system components including memory subsystems and peripherals.

5.
Familiar with Microprocessor and/or DSP instruction sets and how low level driver software integrates into SOC architecture.

6.
Familiar with HDL languages, simulation tools and testbench design, low level assembler languages and C, or C++, scripting languages

7.
Good English and communication skills; will need frequent communication with foreign team.

8.
Experience related to stream processing, video/audio decoding, process technology and reliability qualification is a plus

9.
Experience with a high-level verification language such as System Verilog or Specman is preferred

如果你感兴趣 请联系我

msn : morningjeffdight@msn.com

您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条


小黑屋| 手机版| 关于我们| 联系我们| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-12-29 04:47 , Processed in 0.014868 second(s), 7 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表