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[资料] Programmable System-on-Chip (SoC) for Silicon Prototyping

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发表于 2011-1-21 14:41:59 | 显示全部楼层 |阅读模式

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本帖最后由 fly123456 于 2011-1-21 14:45 编辑

bstract                                                                                                                                                                                               
This paper presents a Programmable SoC (System-on- Chip) design methodology which integrates multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced by sharing a common SoC platform. In this implementation, an integrated SoC platform is comprised of eight SoC projects. When these eight SoC projects are designed separately, the total area is approximately 143.03mm^{2}, while the area of the integrated platform is about 24.43mm^{2}. The area reduction is significant, so is the fabrication cost. Once the integrated platform chip is fabricated, three programming schemes are carried out to allow the integrated chip to act as the individual SoC design projects. A test chip is designed and implemented using the TSMC 0.13um CMOS generic logic process technology.

Programmable System-on-Chip (SoC) for Silicon Prototyping.pdf (506.95 KB, 下载次数: 61 )
发表于 2011-1-21 15:26:00 | 显示全部楼层
谢谢分享!
发表于 2011-1-23 17:29:43 | 显示全部楼层
可惜只是一片论文。
发表于 2011-1-25 04:50:07 | 显示全部楼层
Good for reference.
发表于 2011-1-26 12:08:02 | 显示全部楼层
谢谢啊
发表于 2011-1-26 18:39:45 | 显示全部楼层
感謝大大的分享
发表于 2011-1-28 13:58:21 | 显示全部楼层
thanks for sharing
发表于 2011-1-31 15:06:20 | 显示全部楼层
thanks!!!
发表于 2011-2-11 10:34:32 | 显示全部楼层
buocuo a,duo xie a
发表于 2011-3-11 23:49:45 | 显示全部楼层
谢谢分享!
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