ModelSim SE 6.0 仿真出现问题，求高手指点

robin2011

在Xilinx ISE6.2i下利用模板，用VHDL语言做了一个简单的计数器，安装好ModelSim SE 6.0，想进行仿真时，出现如下错误，求高手指点，问题出在哪里？库文件我编译过，modelsim.ini文件我也修改过了！

# Reading C:/Modeltech_6.0/tcl/vsim/pref.tcl
# //  ModelSim SE 6.0 Aug 19 2004
# //
# //  Copyright Mentor Graphics Corporation 2004
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do TestWave.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity fourbitscounter
# -- Compiling architecture behavioral of fourbitscounter
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity testwave
# -- Compiling architecture testbench_arch of testwave
# -- Compiling configuration fourbitscounter_cfg
# -- Loading entity testwave
# -- Loading architecture testbench_arch of testwave
# -- Loading entity fourbitscounter
# vsim -lib work -t 1ps TestWave
# Loading C:\Modeltech_6.0\win32/../std.standard
# Loading C:\Modeltech_6.0\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.0\win32/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_6.0\win32/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_6.0\win32/../std.textio(body)
# Loading C:\Modeltech_6.0\win32/../ieee.std_logic_textio(body)
# Loading work.testwave(testbench_arch)
# Loading work.fourbitscounter(behavioral)
# .wave
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Failure: Simulation successful (not a failure).  No problems detected.
#    Time: 1 us  Iteration: 0  Process: /testwave/line__74 File: TestWave.vhw
# Break at TestWave.vhw line 177
# Simulation Breakpoint: Break at TestWave.vhw line 177
# MACRO ./TestWave.fdo PAUSED at line 13