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80资产
1.A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR,
O'Donoghue, K.A. Hurst, P.J. Lewis, S.H. Univ. of California, Davis, CA, USA
2.A self-calibrating 16 bit 6 μs CMOS audio ADC, Gotoh, J. Satoh, T. Kishigami, H. Iida, T.
Toshiba Semicond. Syst. Eng. Center, Kawasaki
3.Li-ion battery management chip for multi-cell battery pack
Yidie Ye Chen Chen Jin Jin Lenian He Inst. of VLSI design, Zhejiang Univ., Hangzhou |
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