整理分类板——数字相关职位——上海北京成都

carrie_kthr

Carrie
=======================================
Shanghai Key-Team Human Resources Consulting Co.,Ltd
Add: Room 1310, Huashen building , No.1085 Pudong South Road, Shanghai China
Tel: (86)021-61023600-25
Mobile86)139 1607 0643
Email: carrie-hu@kthr.com  
MSN:mimmimhu@msn.com
LINKIN:  http://cn.linkedin.com/pub/carrie-hu/27/971/74b
http://www.kthr.com



为了大家更好的找到自己的符合的职位机会现分类如下：
1数字IC设计(资深/资浅）职位（有的是设计团队建设，所以是资深资浅的都需要的哈）
2 数字ic验证职位
3设计管理职位
jd 如下：
第一大类数字IC设计(资深/资浅）职位
1.

(Sr/jr) ASIC Design Engineer

Job Duties:  

Responsible for DTV/STB multi-format video codec hardware module development and support. This video codec hardware core will worked together with embeded MIPS/ARM CPU to implement real-time high-definition encoding, decoding and transcoding functions of input bitstreams or video sequence.

Qualifications:  

1.B.S/M.S degree in Computer Science or Micro-electronics or equivalents

2.Be familiar with design flow for ASIC chip design, skillful in RTL coding, synthesis and timing analysis

3.Be Familiar with video compression/decompression algorithms and multimedia applications.

4.Good knowledge in embedded system design.

5.Team player and self-driven.

6.Fluent in written and spoken English.

7.Any of the followings will be a good plus and preferred:

8.Have 2+ years experience in hardware development for video decode/encode or related projects.

9.Have skills in FPGA development

10.Skillful in C/C++ programming language.

11.Have certain knowledge on SoC HW and DSP.

2.

(Sr/jr). IC Logic Design Engineer

Job Duties:

(Moving toward a central SoC-Infra/CPU team to support both STB/DTV development and due to the urgent request from Kronos project, need to move SoC-infra expansion quickly. We need to add four person for the following –

(1)One senior to own PMAN builder

(2)One senior to own PMAN simulation

(3)One senior to own DDR3-Phy/PCTL of C40 and Kronos project

(4)One senior to own overall IP2055 for Kronos project)

Duty: Participate in SOC logic design, simulation, Synthesis and timing analysis. Chip bring up, support Validation Team, SW and FAE team. Field support Customer at special urgent case.

Qualifications: (Education, Experience, etc.)

1.Education: Major in EE or related, Master or above;

2.Familiar with Verilog and VHDL;

3.Knowledge of computer architecture, ASIC design flow, HW system;

4.Three years of experience of IC logic design for peripheral interface;

5.Good personal characteristics as an employee, good communication ability and co-work sprit;

6.Good communication and interpersonal skills.

3.

VLSI Sr/jr SOC Engineer

Job Responsibilities:

1.Reporting to the SoC manager, the candidate is expected to be responsible for following tasks:

2.Develop state of art 45nm complex media processor SoC products with embedded cpu, memory controller, media processor and various mixed signal IPs

3.Work with other cross functional teams in China and overseas to specify, design, validate and improve SoC quality and timeliness to production

4.Participate in SoC architecture definition, SoC integration and verification

5.Create and optimize DFT structure, STA constraints, pad & package selection

6.Work with physical design team to ensure a successfully implementation until tape-out by performing RTL rule check, LEC and power analysis etc

Job Requirements:

1.Bachelor degree in Electrical Engineering or related area, MSEE is preferred.

2.3 years or above experience in ASIC/complex SoC design or verification.

3.Familiar with hardware description languages such as Verilog, System Verilog and VHDL

4.Knowledge of script language, such as Tcl, Python, Perl are required

5.Familiar with IC design & verification tool flow with hands-on experience in DC, PT, NC-Sim and/or Spyglass

6.Good English and communication skills; will need frequent communication with foreign team.

7.Experience related to video/audio decoding, process technology and reliability qualification is a plus

4.

Sr/jr. Audio Design Engineer

Job Duties:

1.Toplevel integration and verification of IP deliveries

2.interact closely with the Audio IP team (Freiburg, Germany)

3.Gate Level Synthesis of IP deliveries with constraining, timing analysis, logic equivalency check

4.Interact closely with the Physical Design team on floor planning and timing issues

5.Support frontend and backend team through the whole design flow until tapeout (in Freiburg, Germany and in Shanghai)

Qualifications: (Education, Experience, etc.)

1.Bachelors/Masters degree in Engineering (Electronic Engineering) or equivalent

2.Experience in standard EDA Tools and Methods (Design Compiler, RTL Compiler,
Primetime etc.)

3.experience in RTL coding (Verilog) and verification

4.Candidate must be able to work independently and interface with various groups

5.Spoken language: English fluent

6.Ability and will to travel

5.

Sr/jr. ASIC Design Engineer Graphic IP  *1

Position Summary

do micro-architecture, rtl coding, simulation and sythesis flow of graphic pipe-line etc.

Job Location

ShangHai, P.R.C

Responsibilities

1.Do micro-architcture based on the architecture spec.

2.Develop the RTL code based on the micro-architecture   

3.Simulation flow and FPGA verification

4.Synthesize after RTL freeze

5.Work with back end teams to do time closure

6.Verify functions

7.Provide support for production issues

8.Prepare documents

Qualifications

1.Master degree or above, major in EE,CS or related.

2.2 - 10 years on front end logic design

3.Good skill in RTL coding, simulation, synthesis and timing analysis;

4.Strong hardware knowlege of computer architecture.

5.CPU/DSP, Video/digital media, or graphic pipe-line design experience is required.

6.Knowlege in computer graphics is a good plus.

6.

Sr/jr. ASIC Design Engineer Graphic IP
*2

Position Summary

do micro-architecture, rtl coding, simulation and sythesis flow of graphic pipe-line etc.

Job Location

ShangHai, P.R.C

Responsibilities

1.Do micro-architcture based on the architecture spec.

2.Develop the RTL code based on the micro-architecture   

3.Simulation flow and FPGA verification

4.synthesize after RTL freeze

5.Work with back end teams to do time closure

6.Verify functions

7.Provide support for production issues

8.Prepare documents

Qualifications

1.Master degree or above, major in EE,CS or related.

2.2 - 10 years on front end logic design

3.Good skill in RTL coding, simulation, synthesis and timing analysis;

4.Strong hardware knowlege of computer architecture.

5.CPU/DSP, Video/digital media, or graphic pipe-line design experience is required.

6.Knowlege in computer graphics is a good plus.

7.

Architecture Design Engineer Graphic IP
*2

Position Summary

Do 2d/3d graphic architecture design, architecture moduling, test-plan and test-case, hw verification and sw-driver development support.etc.

Job Location

ShangHai, P.R.C

Responsibilities

1.Do architecture design based on the graphic standard.

2.Develop the architecture module based on the architecture spec.  

3.Write test-plan.

4.Develop the test-case.  

5.Support hw verifications.  

6.Support sw-driver development.

7.Tuning the performance of graphic pipe.

8.Prepare documents   

Qualifications

1.Master degree or above, major in CS,EE or related.

2.2 - 10 years on graphic/video architcture design, graphic driver/application design.

3.Good skill in C/C++, Familiar with perl/pythong is a good plus;

4.Knowlege of computer architecture, OpenGL/DX is prefered.

5.Knowlege in rtl coding is a good plus.

8.

IC logic Design Engineer(Various Levels)

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Job Duties:
IC logic design(Front End)for Video Quality Processing ICs or SOCs(System on Chip), including Video Algorihm development Verilog RTL coding, Syathesis, StatiTiming Analysis, Integration and Verification, FPGA emulation adn C/C++ Modeling

Qualifications: (Education, Experience, etc.

1.Education: Major in EE or related, Master or above.

2.Familiar with EE logic design flow, such as RTL coding, simulation and synthesis.

3.can write C mode and RTL to implement algorithms.

4.Working experience preferred, but not a must.

5.Familiar with TV system and video processing algorithms is preferred, but not must

6.Good personal characteristics as an employee good communication ability and co-work sprit

9.

Digital design engineer

Responsibility:

Participate in mix-signal IC development high speed mix signal products, working with multi-site engineers on different functions such as analog design, application, product evaluation and layout. The incumbent is expected to contribute to signal chain understanding/partition, algorithm development, design, verification, synthesis, timing and power analysis. And he/she is also required be able to understand the inputs from application engineers to translate real world issues to design requirements. Some basic lab skill to work with product evaluation engineers and understanding real silicon issue is also needed.

Requirement:

1.MSEE or above in EE related majors

2.At least 2-3 years working experience on RTL related design, verification and implementation for FPGA or ASIC. Real mixed signal ASIC experience is preferred. High speed design experience is a strong plus but not necessary required.

3.Knowledge on signal processing is a strong plus. The candidate should know well on sampling theory, filter design, and some of algorithm development skills.

4.Have FPGA or real silicon experience and have chance to look at silicon functions and performance with good silicon debugging skills.

5.Have basic system understanding of converters/PLL or at signal chain level.

6.Self motivated, result oriented, team player and good communication skills.

7.Solid problem solving skills and leadership experience are appreciated.

8.Good spoken and written English

10.

Senior Digital Design and Verification Engineer

Job Responsibilities:

1.Participate in the mixed-signal product development, including digital design, verification, and implementation.

2.Lead to define the product architectures, determine design approaches and parameters

3.Digital signal processing design and verification

4.Top-level integration and verification

Requirement:

1.MSEE or PhD in EE or microelectronics

2.+3 years working experience in RTL design and verification

3.Knowledge on communication system or signal processing is a strong plus

4.Experience with mixed signal design or integration is preferred

5.Familiar with digital design flow and tools, can use synopsys dc/dftc/pt/formality, cadence nc_verilog

6.Self motivated, result oriented, team player and solid communication skills

7.Good spoken and written English

11.

ASIC Engineer of SOC and Video system *1

SOC design

1.SOC methodology define and control

2.Lead and audit block level synthesis and timing closure

3.Top level synthesis

4.Top level STA (define SDC and be responsible to timing signoff)

5.Understand DFT flow, can do necessary support

Video design

1.IP level Micro-architecture, RTL Design, Verification, Synthesis and timing closure.

2.Solid knowledge and experience on video block design and debug

3.Top level architecture, including clock/reset structure, address mapping, bandwidth analysis, etc

Requirements:

1.Must have:

2.BSEE Degree or above

3.3 or 5 years of experience in ASIC design

4.Familiar with industry synthesis/STA/formal tools

5.Familiar with at least one of script language such as perl/tcl/shell

6.Solid RTL design experience, better in video system

7.Self-motivated in solving problems

8.Good communication skills and fluent in English.

9.Good team player

12.

高级)数字芯片设计工程师 成都

岗位职责：

1.LSI的逻辑电路设计;

2.IP整合，合成，验证和修正；

3.综合、静态时序分析；

4.FPGA平台的搭建及基于FPGA的系统验证；

5.系统整体验证及调试，芯片的测试等。

任职要求：

1.微电子/电机/电子工程或相关专业本科、硕士及以上学历;

2.3年或7年以上IC设计工作经验，具有视频，通讯等芯片设计经验；作为Leader开发过一个项目者更佳;

3.熟悉数字电路正向设计，包括Verilog-HDL硬件描述、综合、仿真等;

4.熟悉C语言编程；

5.能熟练使用Xilinx与Altera FPGA开发工具;

6.熟悉逻辑综合，时序分析，Verilog仿真等IC开发环境。

13.
（高级）数字芯片设计工程师 上海

The responsibilities & authorities of IC design (senior) engineer for STB logic design is: logic design, RTL coding, verification, synthesis, timing analysis, test specification definition, system integration and FPGA verification for STB LSI.

Requirements:

1.An university degree in electronics engineering or equivalent, master degree is preferred;

2.Knowledge and experience in digital logic circuits, electronic circuits and computer engineering;

3.Knowledge in MPEG-2/H.264 related video standard is preferred;

4.Experience in FPGA setup is preferred;

5.Experience in STB LSI is preferred;

6.Good communication skills, English language proficiency.

14.

IP and Technical Sales Engineer

Job Function:

1.To drive business decisions on XX IP strategy (IP roadmap) and its implementation (make-or-license from third party)

2.To provide the necessary high-quality, high performance IPs (e.g. libraries, design building blocks) to XX customers and define the related business models

3.To provide the high-quality, fast turn-around time IP solution for XX customers and the related business models

4.To establish foundry-specific IP relationship with strategic IP vendors and partners.

5.Act as technical support engineer to support sales

Responsibilities:

1.Communicate with customers to understand IP requirements.

2.Provide tools and assist Sales to implement IP and Design Service business cases

3.Continuous improvement of IP Quality system and IP database

4.Provide decision proposals for IP roadmap and implementation

5.Collaborate with Account Mangers and Engineering group to come up with complete technical proposal which satisfies Customer's requirements.

6.Support Account Managers to provide direct technical support and communication with customers.

Requirement:

1.Related major of EE

2.Bachelor above

3.3+ years design experience

4.Teamwork, dedication, strong communications and interpersonal skills

5.Fluent oral and written English is plus

15.

IP Development Engineer

Job Duties:

Digital design engineer
working on security and/or transport design modules.
Work will include verilog digital design, verification and validation duties.
Digital design duties will include coding in verilog language, synthesizing verilog to gates and FGPA targets using synopsys and cadence tool sets, designing and inserting DFT test support functions as needed, running integrity checks for the system (lint/cdc/logical equivalence) .
Verification duties will include development of testbenches written in verilog, system verilog or OVM test language, development, analyses optimization of testcases.
Duties will also include integration and support functions to ensure proper integration of the IP into the target SoC device.
Duties will also include execution and support for validation activities to ensure proper operation of the function within the SoC after silicon comes back.

Qualifications: (Education, Experience, etc.)

MSEE with 1 to 4 years of related experience

16.

IC Architecture Engineer

Job Duties:

Do C-modeling, test plan and hardware verification of the assigned graphics blocks.

QualificationsEducation, Experience, etc.)

1.Education: Master degree or above, major in CS,EE, or related.

2.Experience: Experience on hardware c-modeling, 3D graphics driver, and/or 3D graphics application.

3.Knowledge of/Skills and AbilitiesBe familiar with hardware c-modeling;Good skill in C/C++ coding;Knowledge of computer graphics, OpenGL, and/or other 3D standards;Knowledge of computer architecture and logic design is good plus

carrie_kthr

奇怪了 怎么word粘到这个上面变成这个样子了

carrie_kthr

1.        
SoC Verification Engineer
Job Responsibilities:
1.        Reporting to Verification manager, the candidate is expected to be responsible for following tasks:
2.        Apply specialist skills and knowledge in both hardware and software to perform Pre-Silicon verification tasks for complex 40nm Media Processor SOC devices
3.        Perform co-verification of processor models and RTL including application software and firmware verification
4.        Support the development of multi abstraction/views to enable a thorough Soc verification from unit level to system level
5.        Participation in the continued development of verification strategies; evaluate and integrate cutting edge verification/emulation methodologies into the tool flow
6.        Work with other cross functional teams in China and oversea to specify, verify and improve SoC quality and timeliness to production
Job Requirements:
1.        Proficient and experienced with the C/C++ program.
2.        Bachelor degree in Electrical Engineering or related area, MSEE is preferred.
3.        3 years or above experience in ASIC/complex SoC verification. Some RTL design/modeling experience is a plus.
4.        Experience of SOC designs with embedded processor cores and their integration with other system components including memory subsystems and peripherals.
5.        Familiar with Microprocessor and/or DSP instruction sets and how low level driver software integrates into SOC architecture.
6.        Familiar with HDL languages, simulation tools and testbench design, low level assembler languages and C, or C++, scripting languages
7.        Good English and communication skills; will need frequent communication with foreign team.
8.        Experience related to stream processing, video/audio decoding, process technology and reliability qualification is a plus
9.        Experience with a high-level verification language such as System Verilog or Specman is preferred



2.        
Verification Engineer
Responsibilities:
This individual will be a member of methodology/verification team.
Responsibilities will include developing verification environment; developing test plans for and verifying the function of ASIC; hands-on implementation work for every aspect of ASIC verification, working closely with the system group, architects, design and verification teams. The successful candidate should have experience going through at least one complete and successful ASIC design/verification cycle from architecting and creating ASIC test environment to full completion of the verification work. The candidate also needs to have a full understanding of design using Verilog and working experience with SystemC. A strong communication skill in both Chinese and English is required.
Qualifications:
1.        2+ years of ASIC verification experience, complex SOC verification experence is preferred
2.        Strong programming skills in C/C++
3.        Knowledgeable in Verilog/Verilog-PLI/SystemC/SystemVerilog
4.        Responsible for implementation of verification environment and generation of high quality test cases.
5.        BS/MS EE, CE or CS


3.        
Senior / Design verification Engineer
Job Description and Responsibilities:
1.        Responsible for logic verification of memory products.
2.        Generate test plan and test vectors according to product spec.
3.        Generate Random enginee and coverage group by system verilog/script.
4.        Responsible for the developments of specified flash memory products or embedded flash IPs.
5.        Support the design kits include verilog model sythesis lib generation and of embedded flash IPs
Key Competency Requirements:
1.        Basic IC design and verification methodology.
2.        Experience in memeory macro modeling, verilog simulation or synthesis lib generation
3.        Knowledge of non-volatile memory circuits and architecture is a definite advantage.
4.        Tools used may include Verilog, HSPICE/HSIM, Cadence Design Entry, Synopsys synthesis tools, P&R tools, IC layout tools, or other equivalent tools
5.        Education and Experience Required:
6.        Bachelor degree or above in EE
7.        3+years logic verification experience is preferred.
8.        Preferred- Memory (especial Flash memory) knowledge.
9.        Advanced verification methodology knowledge is preferred.
4.        
Senior Validation and Application Engineer
Department: Program and Platform Engineering
Description:
As a member of our test team, this individual would be responsible working with designers and architects to plan and execute verification and validation of ASIC and IP blocks.
Duties and Responsibilities:
1.        Responsible for understanding the expected functionality of logic blocks
2.        Developing test FW and software
3.        Debug hardware and software issue
4.        Implement validation automation system
5.        Maintain proper documentation bugs or issues
Qualifications:
1.        Prefer Master in EE or Computer Science with at least three years of experience
2.        Minimum required skills: Firmware, ASIC, Hardware, ARM or DSP processors, device drivers
3.        Coding skill in C/C++, Assembly, scripting languages
4.        In-depth knowledge of SoC/ASIC verification flow with emphasis in coverage driven verification/validation methodology.
5.        Depth and breadth of knowledge on industry standard IO protocols: UART, SPI, I2C, I2S, flash memories, SRAM and DRAM.
6.        Good communication skills

carrie_kthr

第三类 设计管理类
1.        
Design Manager/Sr. Staff IC designer
Responsibility:
Lead team and/or work as individual contributor to design and implement the company’s cutting-edge SoCs, includes;
1.        SoC Architecture design, partitioning and interface definition
2.        Block level design, RTL coding, and verification
3.        Specify IP requirements according to product specification, seek and evaluate third party IPs.
4.        Design reviews and verification coverage analysis
5.        Run Synthesis, STA, formal check, and FPGA emulation
Requirement:
1.        MSEE /MSCE with above 5 years(8 years for manager) experience on IC design, or equivalent
2.        Strong skill on Verilog HDL, and matlab/C/C++
3.        Multiple projects experience on IC design from specification to netlist.
4.        Experience on complex SoC hardware/software co-design
5.        Well organized, strong communication skill, work smart, and result oriented
6.        Experience on one or more of the following is a plus:
a.     Hardware architecture, organization, design and integration of RISC or DSP
b.     Mapping algorithm to RTL for Digital and wireless Communications
c.      DTV multimedia system, such as audio/video processing, A/V synchronization, and error handling
d.     Low power design technology
e.     LEC, DFT and STA (timing closure)
2.        
System hardware manager/Staff hardware Engineer
Responsibility:
1.        Reference design for chip target application, including system design, schematic design, PCB layout, BOM generation, board debug and bring up
2.        Board Design and debug for FPGA prototyping and engineering chip validation
3.        Working closely with customer’s R&D teams on customer hardware design reviews and performance tuning
4.        Investigate the system solution of Customer’s target application. Collect, validate and feedback product market requirement to Marketing and R&D team  
Requirements:
1.        MSEE with 5 years experience or equivalent
2.        Hands on Experience on RF and mixed-signal board design and debug, especially in cell phone application
3.        Experience with designing for EMC and debugging related issues on RF interference and EMI
4.        Hands on experience on FPGA prototyping, chip validation board design and debug, reference board design and bring up  
5.        Hands-on development experience using I2C/GPIB/SPI/USB is a plus
6.        Strong communication skill, team work oriented, result oriented
7.        Fluent in English
3.        
Technical (Assistant) Manager-TV Engine 技术 成都
Job Descriptions:
1.        Lead MEMC/TVE development team in CD. Duties include participating in the development and support of the existing and new modules for functions such as digital design, verification, and validation.
2.        The team lead/manager will lead a team working with the Shanghai teams and be responsible for the day to day activity of the team members providing technical and managerial level direction, coordinating interaction with other team members in Shanghai, driving and managing integration and support activities with the MEMC/TVE team for the related IPs.
Job Specifications:
1.        BS/MS in EE/CS required, MS with 5+ years of experience in related area and BS with 7+ years of experience in related area;
2.        Strong experience in Verilog, C/C++ and perl skills;
3.        Extensive hardware experience in designing and validating image processing.;
4.        Management experience in multipartite company which focus on electronic technical is a plus;
5.        Self-motivated and strong team work skill;
6.        Good communication skill in English.
4.        
Manager Audio Design
Job Duties:
1.        Support frontend and backend team through the whole design flow until tapeout (in Freiburg, Germany and in Shanghai)
2.        Coordinate Audio Integration Team in SHA
3.        Represent Audio IP-Team in SoC projects
4.        Toplevel integration and verification of IP deliveries
5.        Interact closely with the Audio IP team (Freiburg, Germany)
6.        Interact closely with the Physical Design team on floor planning and timing issues
7.        Interact closely with the DfT team during integration and Test Program Development
Qualifications: (Education, Experience, etc.)
1.        Bachelors/Masters degree in Engineering (Electronic Engineering) or equivalent
2.        Experience in standard EDA Tools and Methods (Design Compiler, RTL Compiler, Primetime etc.)
3.        Experience in RTL coding (Verilog) and verification
4.        Experience in coordination of a group of engineers would be an advantage
5.        Candidate must be able to work independently and interface with various groups
6.        Spoken language: English fluent
7.        Ability and will to travel.
5.        
Director of Validation Team
Position Summary
This position is responsible for managing and leading a team of engineers to provide silicon validation for both Set-Top-Box and TV SoC and Discrete chips.
Job Location
This position is located in Shanghai, China
Responsibilities
1.        Lead a team to provide system implementation. The team provides Platform schematic, Printed-Circuit-Board (PCB) layout, platform production and debugging.
2.        Be able to communicate with internal developers in logic design, circuit design and software implementation.
3.        Be able to work with our production teams in supporting manufacturing activities.
4.        Be able to work with field teams to provide needed supports to their needs.
Qualifications
Required:
1.        MSEE, BSEE with MBA or Above
2.        At least five year of experiences in Set-Top-Box Industry is very desirable
3.        Experience managing and leading large engineering teams
4.        Excellent verbal and written English and Chinese language skills
5.        Strong presentation and coordination skills
6.        Strong organizational skills, team work capability and multicultural way of thinking


Preferred:
1.        Have system design experience.
2.        Be familiar with software implementation
3.        Have logic design experiences.
4.        12 plus years of experience in Semiconductor industry and experience in silicon validation, silicon verification, system implementation, or all of them
6.        
Integration Circuit Engineer × 2
Job Duties:
Be an active member of the Development organization.--Support product manager on IC/Macro spec definition;--Oversee the integration design flow;--Leading design review meetings;--Circuit / Process consultancy
1.        Design IC's Power Ground system;
2.        Design IC's Clock system;
3.        Define the IC's ESD/Latch-up design rule;
4.        Oversee and Guide-line Layout engineer on Macro integration, noise immunity and Verification activities;
5.        Working with Layout engineer on Timing closer;
6.        IC's Circuit database management;
7.        Maintain knowledge on Macros (internal and external sources), Tools, design methodologies and flows;
8.        Macro validation, characterization and customer support, including debugging and analysis report
9.        Writing internal design documents, design reports, review repot, evaluation plans/docs...
10.        Support:--Provide design documentation, descriptions and information to application engineers, field application engineers, product engineers, and customers.--Contribute test specifications and support evaluation of the design in coordination with application and product engineering.
Qualifications: (Education, Experience, etc.)
1.        Education: Bachelor / Master degree or Above;
2.        work Experience: 5+ years experience on circuit design or chip integration design.
3.        Expertise / Skills:--well known IC integration flow;--Good knowledge in CMOS digital circuit, timing and power analysis;--Good knowledge in digital IC design EDA tools, such as ncsim, Design Compiler, Primetime, Astro/ICC etc;--Experience in Circuit design or Verilog coding.--Familiar with Script language (Perl / TCL);--Fluent spoken and written English (frequent communication with overseas teams).
7.        
Sr. IC Physical Integration Engineer
Job Duties:
To execute circuit and final physical implementation related technical tasks in projects including, but not limited to IP ownership and integration, ASIC physical systems and circuit implementation, ASIC characteristics verification and validation and device interconnect verification.
Qualifications: (Education, Experience, etc.)
1.        Bachelor / Master degree or Above.
2.        5+ years experience on physical implementation and circuit design.
8.        
Staff IC Physical Integration Engineer × 2
Job Duties:
To lead, manage and guide ASIC projects in the final physical implementation stage including standard design steps, organizing reviews, tape-out proceedings and all other topics within the project and scope.
Qualifications: (Education, Experience, etc.)
Bachelor / Master degree or Above.7+ years experience on physical implementation and circuit design.
9.        
   Technical Solution Manager/Project Manager
1.        Familiar with IP and IC design
2.        Strong communication skills
3.        Familiar with IC market
4.        4+ years of related experience
10.        
   IP manager
1.        Strong background in IP, knows IP industry
2.        Strong communication skills
3.        4+ years of IP marketing experience
11.        
Marketing manager
1.        Strong marketing background in IC industry
2.        Solid IP knowledge
3.        Strong communication skills/presentation skills/English
4.        4+ yrs of marketing in IC industry

wangjunweiair

dddddddddddddddddd

carrie_kthr

dingdingding a

carrie_kthr

新增ASIC职位 欧美知名半导体公司，产品方向为无线通讯


Sr. ASIC design engineer
Job Description:
1.         Will use state-of-art ASIC design tools and flow to develop low power SOCs
2.         ARM based SOC Architecture / Micro-Architecture / Implementation
3.         ARM based SOC HW/FW co-design
4.         Logic design for peripherals for ARM SOC.
5.         Low power system design, RTL design and post-layout power analysis
6.         Interface with backend team for chip implementation
7.         Chip level and block level floorplan
Job Requirements:
1.         Successful ARM-based SOC project development experience
2.         Deep understanding of ARM/DSP based SOC architecture, bus, peripherals and security
3.         Deep understanding of low power system architecture, RTL design, power simulation and analyze.
4.         Deep understanding of micro-electronics devices and logic design
5.         Familiar with chip verification environment and flow
6.         TCL/Perl script, asm/C/C++ programming, good documentation ability
7.         Track record of planning and delivering own work completely and on time
8.         Takes initiative and sets high goals
9.         Smart and confident
10.         Self starter & ability to work in a team environment as an individual contributor
11.         Strong skill in problem analysis and fixing
12.         Good English skills
Education & Work Experience:
1.         3-5 years of work experience in chip architecture / micro-architecture / RTL design / synthesis / DFT/ STA analysis.
2.         Familiarity with backend Place & Routing design flow
3.         Strong knowledge of CMOS device and circuit fundamentals
4.         Strong skills in document reading. Skills in Tcl/Perl script programming

carrie_kthr

Title: Senior IC design engineer/Project manager/AE
Job Description:
Work with customer to define detail SoC specification
Work with the Architect to design the system bus architecture of SoC, Implement the system bus
IP verification and integration
System level integration and verification
Back-end design related support

Required Skills:
MSEE Degree or equivalent
Knowledgeable in ASIC design methodology
Minimum 5 year experience in the hands-on IC Design
Be familiar with ARM process and AHB, AXI protocol.
Familiarity of FPGA prototyping

zhanweisu27

富记那个好显眼啊

carrie_kthr

叮叮叮 顶顶顶