上海12月数字IC职位信息

KT胡运旺

Connie Wang Assistant Consultant Key-Team Human Resources Consulting Co.,LtdAdd: Room 1310, Huasheng building , No.1085 South Pudong Road , Shanghai China Tel:  021-61023600-21 Mobile: 13774287934 Email: [url=mailto:digital@kthr.com]digital@kthr.com[/url] MSN:  conniewang1987228@hotmail.com Website:www.kthr.com 有意请联系我！！！ No.54 Physical design engineer 上海 职位介绍： DESCRIPTION OF FUNCTION & RESPONSIBILITY: 1. Implement APR from netlist to gds to close timing and routing 2. Build high efficient PG mesh to meet IR-drop and EM requirements 3. Fix SI effect 4. Perform ECO and metal spin 5. Support die size estimation 6. Develop utilities/scripts to improve design flow 职位介绍： QUALIFICATION (DETAIL): Education: BSEE or MSEE Experience: 1. Knowledge of any part of the process from netlist handoff to tapeout is a MUST: Floorplanning Power planning and signoff Placement, CTS and routing SI effect analysis and fixing Physical verification 2. Hands-on experience on above items is preferred. 3. Scripts development in Perl and TCL No.130 ASIC P&R engineer 上海 职位描述 In this role you will be responsible for chip/block level floorplanning, power planning, timing-driven place and route, congestion analysis and repair, clock tree synthesis, timing closure and physical verification (DRC/LVS). Perform circuit custom layout design and power planning. 职位要求： Job Requirement: 1. Experience in ASIC physical design (place and route, DRC/LVS, power distribution, etc.) 2. Be familiar with PR tools such as SOCE/Austra. 3. Be familiar with chip tape out flow. 4. Experienced in circuit custom layout design. 5. BS/MS degree in Electrical Engineering, or science related subject. 6. Good communication and teamwork skills. No.130 IC Logic Design Engineer 上海 Job Duties: Micro-architecture design, RTL coding, simulation and verification of the assigned graphics block; should be also responsible for the synthesis and timing check of the block. Qualifications Educations, Experience, etc.): 1.Education: Master degree or above, major in Micro-electronic,EE, CS or related. 2.Experience: Have experience on SOC chip design. 3.Knowledge of/Skills and Abilities·Be familiar with IC logic design flow;·Have good skill in RTL coding, simulation, synthesis and static timing analysis;·Have strong hardware knowledge of computer architecture, Know-how in computer graphics is preferred;·GFX Chip design experience will be a good pls. No.130 IP Development Engineer 上海 Job Duties: Digital design engineer working on security and/or transport design modules. Work will include verilog digital design, verification and validation duties. Digital design duties will include coding in verilog language, synthesizing verilog to gates and FGPA targets using synopsys and cadence tool sets, designing and inserting DFT test support functions as needed, running integrity checks for the system (lint/cdc/logical equivalence) . Verification duties will include development of testbenches written in verilog, system verilog or OVM test language, development, analyses optimization of testcases. Duties will also include integration and support functions to ensure proper integration of the IP into the target SoC device. Duties will also include execution and support for validation activities to ensure proper operation of the function within the SoC after silicon comes back. Qualifications: (Education, Experience, etc.) MSEE with 1 to 4 years of related experience No.130 IP Development Team Lead 上海 Job Duties: 1. Lead security/transport/network development team in Shanghai to augment and offload Austin/Haifa development team. Duties will include the integration of the transport and security IP into the STB and DTV SOCs and provide first level of support for the IP. Duties will also include participating in the development and support of the existing and new modules for functions such as digital design, verification, validation . 2. The team lead/manager will lead a small team of people working with the Austin and Haifa teams and be responsible for the day to day activity of the team members providing technical and managerial level direction, coordinating interaction with other team members in Austin and Haifa, driving and managing integration and support activities with the SOC team for the related IPs. Qualifications: (Education, Experience, etc.) BSEE with 10 years experience or MSEE with 7 years related experience. No.130 Staff CAD engineer 上海 Job Duties: 1.Main supporter for FE tools and design methodologh. 2.Be able to take lead position on flow architecture definition and implementation. Make it a high efficient design platform for Trident WW chip design team. 3.Ensure FE design environment sanity for every project. Qualifications: (Education, Experience, etc.) 1.Major in EE/CS with patient conscientious personality. 2.Master with 5 years' project experience on FE field including synthesis and STA etc. 3.Excellent programming skill on Perl/Bsh/Csh/Tcl. 4.Be familiar with UMC/TSMC 65nm/40nm design flow. 5.Good interpersonal as well as communication skills. No.130 VLSI Sr SOC Engineer 上海 Job Responsibilities: Reporting to the SoC manager, the candidate is expected to be responsible for following tasks: 1.Develop state of art 45nm complex media processor SoC products with embedded cpu, memory controller, media processor and various mixed signal IPs 2.Work with other cross functional teams in China and overseas to specify, design, validate and improve SoC quality and timeliness to production 3.Participate in SoC architecture definition, SoC integration and verification 4.Create and optimize DFT structure, STA constraints, pad & package selection 5.Work with physical design team to ensure a successfully implementation until tape-out by performing RTL rule check, LEC and power analysis etc Job Requirements: 1.Bachelor degree in Electrical Engineering or related area, MSEE is preferred. 2.3 years or above experience in ASIC/complex SoC design or verification. 3.Familiar with hardware description languages such as Verilog, System Verilog and VHDL 4.Knowledge of script language, such as Tcl, Python, Perl are required 5.Familiar with IC design & verification tool flow with hands-on experience in DC, PT, NC-Sim and/or Spyglass 6.Good English and communication skills; will need frequent communication with foreign team. 7.Experience related to video/audio decoding, process technology and reliability qualification is a plus No.130 IC Logic Design Engineer (Video R&D) 上海 Job Duties: IC logic design (Front End) for Video Quality Processing ICs or SOCs (System on Chip), including Video Algorihm development Verilog RTL coding, Syathesis, StatiTiming Analysis, Integration and Verification, FPGA emulation adn C/C++ Modeling. Qualifications: Education: Major in EE or related, Master or above. Familiar with EE logic design flow, such as RTL coding, simulation and synthesis. Can write C mode and RTL to implement algorithms. Working experience preferred, but not a must. Familiar with TV system and video processing algorithms is preferred, but not must. Good personal characteristics as an employee good communication ability and co-work sprit No.122 ASIC backend engineer 上海 职位描述： Job Description As the ASIC Backend Engineer, you will be working closely with the front end ASIC team to synthesize the RTL, clean up the timing, go through the backend flows to deliver the tape-out. 职位要求： Strong understanding of backend ASIC design flow, ie synthesis, DFT, floor planning, clock tree synthesis, place and route, SI analysis, timing closure, LVS, DRV. Demonstrated knowledge in integrating analog/mixed signal IPs. Hands on experience in low power design and deep sub micron technology. A self-starter that is motivated and a good team player. BSEE required, MSEE preferred. 3+ years industrial experience. No.129 APR 上海 APR Job function: 1. Floor plan, placement, routing , CTS and timing closure 2. Power,IR SI verifcaiton 3. DRC/LVS verification APR requirement: 1. BS or MS degree in EE or CS related 2. Educational background/experience with logical and physical synthesis, VLSI design, static timing analysis methods and tools, place and route 3. Experienced/interested in one or multiple of Synopsys Astro/ICC, Cadence SOCE 4. Scripting utilizing Perl or Tcl/TK 5. Interested in taking the challenges of 65nm and below physical designs No.16 CAD/digital implementation engineer 上海 BS or above in EE or CS or Physics 1 ~ 3 years related work experience. Strong programming (Perl, TCL, shell script) skills. Back-end ASIC design flow knowledge is preferred. Experienced with common EDA tools flow is preferred Experienced physical design verification is preferred. Basic logic/RTL design and microprocessor knowledge Basic understanding of CMOS VLSI IC design and DFT knowledge No.149 (Sr.) IC Physical DE –COT (高级) 芯片后端设计工程师-COT 上海 Job Descriptions: 1.Physical design from netlist to GDSII; Primarily focus on 90nm/65nm/40nm process technologies and design methodologies; 2.Typical tasks include IO-assigning, Floorplan, Clock tree generation, Place and Route, Static Timing Analysis and physical verification； 3.Support ASIC/COT customer from Physical point of view. Requirements: 1.Bachelor Degree or above, Major in electronic engineering or related field; 2.More than 3 years design experience in System On Chip or Analog IP layout; 3.Strong knowledge of logic design and CMOS technology; 4.Strong knowledge and experience of DRC/ERC/LVS, ESD, SSO(Spice level); 5.Dedicated and hard working with good interpersonal and communication skills; 6.Good English writing and speaking are required and Japanese speaking is a plus; 7.Self motivated to learn new technology and methodology. No.149 (高级)数字芯片设计工程师(DAV / (Sr.)IC DE(DAV) 成都 Responsibilities: The responsibilities & authorities of IC design engineer are product oriented digital IC design, detail as below: 1.         Synthesizable RTL level design and coding; 2.         Design verification and debug, integration of IP into a large system-on-chip; 3.         Assist with synthesis and static timing analysis; 4.         FPGA verification setup and debug; 5.         Test bench design to assist in system level validation, and designing chip for ATE. Requirements: 1.        Bachelor, Master from Microelectronics/Electrical/Electronics Engineering; 2.        More than 3 or 7 years working experience in IC design, in the field of video, communication, etc, as team leader for one project development is preferred； 3.        Familiar with top-down design of digital circuits, including the Verilog-HDL hardware description, assembly and simulation; 4.        Proficient in C, FPGA developing tools such as Xilinx & Altera; 5.        Familiar with IC developing environments including logic synthesis, timing analysis and Verilog simulation. No.152 Digital layout engineer 上海 Job Summary The Digital Layout Engineer (DLE) plays an essential role in the physical implementation of the top-level functional netlist, resulting in an optimally placed, routed and verified chip layout. He/she also supports and advises the development team and third parties (subcontractors, customers) with respect to the physical development of Analog & Mixed Signal modules used in the IC’s. The DLE has sufficient broad knowledge to co-operate with all other competencies within the project, and establishes and contributes to a co-operative and productive interaction in team working situations. Key Areas of Responsibility 1. Building up, and maintaining knowledge of: • Schematic, symbol, layout and abstract design, physical topologies and design methodologies. • Translating IC specifications to an optimal placement of PMU modules and I/O pads, in close co-operation with the system/IC architect and the customer. • Creating an optimal routing of critical and non-critical signals, supply trunks and clock trees for the complete top-level IC from a functional netlist. • ESD, EMC, supply strategy, clocking strategy, design for test, and related 2. Layout Verification before Tape Out: • Verifying and completing the IC with DRC/LVS checks, chip-finishing and bonding. • Participating in physical design reviews, also in other projects. • Delivering back-annotated data needed for timing verification of modules, both standalone and embedded in top level circuitry. • Properly tagging of IC layout data bases 3. Communication: • Maintain a network of contacts on physical IC design • Contribute to co-operative and productive team atmosphere • Communicate with conciseness in both one to one and group situations. Requirements • BSc-E or MSc-E. • Being knowledgeable on: (1) Data exchange formats: LEF, DEF, TLF, (R)SPF, SDF and GDS2. (2) Synopsys IC compiler (3) Experience in following tools: Place & Route Tools, Skill, Pearl and other script languages, etc. • A pro-active attitude. • Fluent in English

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