SYSTEM-ON-CHIP TEST ARCHITECTURES NANOMETER DESIGN FOR TESTABILITY

robertqi

The advanced topics covered in this book can also be categorized into multiple
sections, with each section consisting of multiple chapters. They are as
follows:
1. DFT Architectures for
Digital Logic Testing (Chapter 2)
System/Network-on-Chip Testing (Chapter 4)
System-in-Package Testing (Chapter 5)
FPGA Testing (Chapter 12)
High-Speed I/O Interfaces (Chapter 14)
Analog and Mixed-Signal Testing (Chapter 15)
2. New Fault Models and Advanced Techniques for
Delay Testing (Chapter 6)
Low-Power Testing (Chapter 7)
Coping with Physical Failures, Soft Errors, and Reliability Issues (Chapter 8)
Software-Based Self-Testing (Chapter 11)
RF Testing (Chapter 16)
3. Yield and Reliability Enhancement
Fault-Tolerant Design (Chapter 3)
Design for Manufacturability and Yield (Chapter 9)
Design for Debug and Diagnosis (Chapter 10)
4. Nanotechnology Testing Aspects
MEMS Testing (Chapter 13)
Resonant Tunneling Diodes, Quantum-Dot Cellular Automata, Hybrid
CMOS/Nanowires/Nanodevices, and Carbon Nanotubes (Chapter 17)
Each chapter of this book follows a specific format. The subject matter of the
chapter is first introduced, with a historical perspective provided, if applicable.
Related methods are explained in detail next. Then, industry practices, if applicable,
are described before concluding remarks. Each chapter (except Chapter 17)
contains a variety of exercises to allow this book to be used as a textbook for
an advanced course in testing. Every chapter concludes with acknowledgment to
contributors and reviewers and a list of references.
Chapter 1 introduces system-on-chip (SOC) testing. It begins with a discussion of
the importance of testing as a requisite for achieving manufacturing quality and
then identifies test challenges of the nanometer design era. This is followed by a
brief overview of some of the IEEE boundary scan and core-based test standards
that are widely used within industry (including 1149.1, 1149.4, 1149.6, and 1500).
SOC examples practiced in industry are shown to illustrate the test challenges we
face today.
Chapter 2 provides an overview of the most important test architectures for
digital logic testing. Three basic design-for-testability (DFT) techniques widely used
in industry are covered first: scan design, logic built-in self-test (BIST), and test
compression. For each DFT technique, fundamental and advanced test architectures
suitable for low-power and at-speed applications are discussed. The remainder of
the chapter is devoted to random-access scan, a promising alternative to scan design
for test power reduction.
Chapter 3 covers fault-tolerant design techniques that are applicable to both SOC
designs and system applications. As the topic is quite broad, care is taken to describe
widely used coding methods and fault tolerance schemes in an easy-to-grasp manner
with extensive illustrations and examples. The chapter lists applications where
the discussed techniques can be utilized.
Chapter 4 is devoted to both system-on-chip (SOC) and network-on-chip (NOC) test
architectures. Various techniques for test access and test scheduling are thoroughly
examined and presented. The chapter includes a discussion of the similarities and
differences between the two as well as examples of each. Industrial designs are
studied to show how these techniques are applicable to SOC and NOC testing.
Chapter 5 describes important test cost and product quality aspects of packing
multiple dies in a system-in-package (SIP). After an introduction to the basic
technologies, specific test challenges are presented. A number of bare-die test techniques
to find known-good-dies are subsequently described. Functional system test
and embedded component test techniques are then presented to test the SIP at the
system level. The chapter ends with a brief discussion of future SIP design and test
challenges related to nanometer technologies.
Chapter 6 addresses the testing of delay faults. The main focus of this chapter is
on testing defect-based delay faults, often called small delay defect testing. Without

zh123456789

谢谢啊

mtwumtwu

good reference for DFT

gaconht

good thanks

gaconht

谢谢啊 !

comway1981

3kkkkkkkkkkssssssssss

comway1981

good reference for DFT

chujn

下来看看，谢谢。

navyhu

thanks a lot
good for u

nslnsl

DFT，不错！！