AMS +elaborate+error

prisnow

直接选用OSS-based netlister选项做仿真，应该就可以解决。 亲测可行。

以下资料摘自"Virtuoso AMS Designer Environment Tutorials"


The AMS cellview-based netlister (the original netlister for AMS Designer) translates
schematic cellviews into Verilog®-AMS netlists, for one cell at a time. The output of a
successful netlisting run is one or more files named verilog.vams, each containing a valid
Verilog-AMS module that corresponds to a schematic cellview, in the lib/cell/view for the cell.
The cellview-based netlister requires that you have ams simInfo in your PDK library.
Cadence’s Open Simulation System (OSS) netlister creates a single netlist of the entire
design hierarchy in the netlist directory. The OSS netlister uses spectre simInfo. You do not
need to add ams simInfo or convert PDKs (as you do if you use the cellview-based netlister).
The Spectre and UltraSim circuit simulators use this netlister.

prisnow

仿真时候选择OSS-based Netlister应该就可以。 亲测可行

yangmxue

用楼主的方法解决了，可以仿真了，还是出现的错误的小伙伴们看看使用的cadence版本和incis版本是不是合适，我用的cadence615和INCISV142