|
发表于 2010-11-24 17:58:23
|
显示全部楼层
回复 8# lihaiqi208
Question:
Did you use the following command card in your simulation deck?
.hdl abc.va $ where "abc.va" is the name of the file that contains the block that is described by Verilog-A language.
As the next step, please check the log file of your Hspice runs.
In the log file, you should see something like the following:
... Invoking the Verilog-A compiler for 'abc.va'
.
.
.
... Synopsys HSPICE Verilog-A Compiler version 1.YYY.ZZZZZZ.
.
.
.
... lic: Release hspiceva token(s)
If all the above shows up, it means your simulator is with the Verilog-A license and can bring up the Verilog-A compiler.
Good luck! |
|