猎头职位：国际知名美资公司招聘ASIC/FPGA设计验证工程师（上海）

emilychen

Note:
-        The job description below is for a Senior ASIC/FPGA Design Verification Engineer
-        Looking for
o        3 Senior ASIC/FPGA Design Verification Engineer
o        6 ASIC/FPGA Design Verification Engineer

Job Description:
Participate in architecture and design verification of complex networking ASIC.  Responsibilities include:
-        Architecture/Micro-Architecture definition
-        Standalone and Integrated functional verification;
-        Documentation and review of Verification architecture and testplans
-        Develop verification environment (models, checkers, packet manager) using Specman/Vera
-        Develop random, pseudo-random and directed tests
-        Establish verification effectiveness using assertion/functional/code coverage and code reviews
-        RTL and gates simulation, debug and root cause
-        Regression triage and debug
-        Formal verification and equivalence checking.
-        Lab debug and design validation

Skills required:
-        Prior significant verification experience on complex ASICs.  
-        Good background in networking concepts.  
-        Experience with Vera/Specman and Verilog.  
-        Chip and system and test experience.  
-        Programming and scripting skills.
-        Good planning skills (well partioned designs, well organized code)
-        Outstanding written and verbal communication skills
-        Capability of critical thinking, challenging design intent

Education:
MSEE with 5+ yrs or BSEE/CS  with 7+ yrs relevant experience

有兴趣的可以加我的MSN聊聊：eimily82117@hotmail.com

dusui

ding 一个

bobosky_sz

谢了啊楼主