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本帖最后由 ic_qiand 于 2010-10-29 23:28 编辑
If you survey hardware design groups, you will learn that between 60% and 80% of their effort is dedicated to verification. This may seem unusually large, but I include in "verification" all debugging and correctness checking activities, not just writing and running testbenches. Every time a hardware designer pulls up a waveform viewer, he or she performs a verification task. With today’s asic and FPGA sizes and geometries, getting a design to fit and run at speed is no longer the main challenge. It is to get the right design, working as intended, at the right time.
Unlike synthesizable coding, there is no particular coding style nor language required for verification. The freedom of using any language that can be interfaced to a simulator and of using any features of that language has produced a wide array of techniques and approaches to verification. The continued absence of constraints and historical shortage of available expertise in verification, coupled with an apparent under-appreciation of and under-investment in the verification function, has resulted in several different ad hoc approaches. The consequences of an informal, ill-equipped and understaffed erification process can range from a non-functional design requiring several re-spins, through a design with only a subset of the intended functionality, to a delayed product shipment.
front-matter.pdf
(206.11 KB, 下载次数: 10 )
1What is Verification.pdf
(235.32 KB, 下载次数: 11 )
2Verification Technologies.pdf
(428.61 KB, 下载次数: 16 )
3The Verification Plan.pdf
(277.02 KB, 下载次数: 14 )
4High-Level Modeling.pdf
(483.26 KB, 下载次数: 12 )
5Stimulus and Response.pdf
(429.03 KB, 下载次数: 10 )
6Architecting Testbenches.pdf
(336.6 KB, 下载次数: 15 )
7Simulation Management.pdf
(286.9 KB, 下载次数: 11 )
back-matter.pdf
(295.23 KB, 下载次数: 10 )
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发表于 2010-10-29 23:25:19
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