一道笔试题

xiaocanmeng

module bishi();
reg signed[3:0]a;
reg [3:0] b;
wire [7:0]z0,z1,z2;
assign z0=(a*b);
assign z1=$unsigned(a*b);
assign z2=$signed(a*b);
initial
begin
a = -3;
b = 4;
#1 $display("a=%d,b=%d,z0=%d,z1=%d,z2=%d",a,b,z0,z1,z2);
end
endmodule
请写出打印输出,并说明理由。