|
发表于 2010-10-16 17:01:54
|
显示全部楼层
Please refer to:
Encounter User Guide,
chapter 16: Synthesizing Clock Trees,
section: Understanding CTS Operation Modes
All these commnads add or remove some pins from clock pins set.
To understand these terms, lets see how clock pins are recognized (I've copied these from the manual):
---------------------------------
Automatic CTS for Gated Clocks
For automatic-gated CTS, CTS traces the clock tree starting from a root pin. The tracing
begins at the root pin, then continues through the buffers, inverters, multi-output cells, and
gated instances to establish the clock tree. The tracing stops at
- A clock pin
- An asynchronous set/reset pin
- An input pin without any timing arc to an output pin
- A user-specified leaf pin or excluded pin
- Data pin of registers (or flops)
- Asynchronous set or reset pin of registers (or flops)
- Enable pins of tri-state instances
After the tracing, CTS builds the clock buffer tree topology to balance the clock phase delay
with inserted clock buffers.
---------------------------------
So:
leafPin:
If we want to force cts to stop at a special pin that is not a clock pin ( for any reason ) and
synchronize this pin with other clock pins, we use leafpin command.
excludedPin:
If we want to force cts to stop at a special pin that is a clock pin or a pin that tracing through it will end up at some clock pins, we use excludedpin command. So the affected pins will not be synchronized with other clock pins.
throughPin:
If we want to force cts to continue tracing through a special pin (that it normally treat the pin as clock pin), we use throughPin command. For example, if we have devided the clock by a DFF, then the D-pin of DFF should be in throughPin list, and the nets that are drived by Q- or QN-pins will act as clocks. Else cts will stop at clock pin of dividing DFF, and the drived clocks will not synchronous. |
|