[求助]有关综合ram的问题，大侠帮忙,

joos

刚学FPGA不久，水平很差，希望高手指点
下面是我写的测试程序，希望把data_sav综合成block_ram，可是老综合成别的用FF和LUT实现的存储器，大侠帮帮忙。用的是synlify pro8.0,ise6.1,片子选的是virtex2v80.
module TEST_RAM(wri,data,clk,rst,dataout,tr_flag);
    inputwri,clk,rst;
    input [7:0] data;
    outputdataout,tr_flag;
   
    reg [7:0]data_sav[15:0] /*synthesis syn_ramstyle="block_ram"*/  ;
    reg  [7:0]data_buff;
    regtr_flag,dataout;
    reg [2:0]tr_state;
    reg [2:0]i;
    reg  [3:0]m;
   
   
    parametertr_stata=3'b000,tr_statb=3'b001,
    tr_statc=3'b010,tr_statd=3'b100;
always @(posedge clk)   
     if(!rst)begintr_state<=tr_stata;
dataout<=1'b1;
tr_flag<=1'b1;
i<=3'b000;
m<=4'b0000;
end
elsebegin
casex(tr_state)
tr_stata:
if(wri)begintr_state<=tr_statb;
end
elsetr_state<=tr_stata;
tr_statb:
begintr_flag<=1'b0;
data_buff<=data;
dataout<=1'b0;
tr_state<=tr_statc;
end
tr_statc:
beginif(i!=7)
begindataout<=data_buff[0];
data_buff<={data_buff[0],data_buff[7:1]};
i<=i+1;end
else
begindataout<=data_buff[0];
i<=3'b000;
tr_state<=tr_statd;
data_sav[m]<=data_buff;
end
end
tr_statd:
begindataout<=1'b1;
tr_flag<=1'b1;
tr_state<=tr_stata;
m<=m+1;
end
default:tr_state<=tr_stata;
endcase
end
endmodule

jingli888ca

你的方法错误.
应该先用Core Gen 产生RAM,再在PAR时加入.综合时,你只能综合一个黑匣子.