SystemVerilog 3.1a
Language Reference Manual
Accellera’s Extensions to Verilog
Abstract: a set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language to aid
in the creation and verification of abstract architectural level models
手册 O(∩_∩)O~ SystemVerilog.pdf(4.05 MB, 下载次数: 85 )