HSIM+VCS的问题

hamony168

做在混合信号电路时，HSIM和VCS可以将verilog描述和spice网表合在一起混合仿真，进行系统验证。但数字部分和模拟部分版图完成后，数字部分生成了SDF文件，模拟部分生成了带寄生参数的spice网表。又合在一起用HSIM和VCS混仿，数字部分结果明显不对，可能是SDF延迟没有加进数字电路。如何解决此问题。望能得到高手指导。

ningwei8027

打酱油，路过，学习一下！

sjjg

sdf没有反标回去吧

alisone

hsim工具如何

alisone

如何合在一起用HSIM和VCS混仿

rockwelleyes

非常感谢

umts2000

回复 1# hamony168


    正在学习混仿，能否分享一下混仿的例子~~~~

xxeerr

VCS反标
Separate Annotations
This example shows separate annotations to distinct portions of a design hierarchy. There is
no configuration file specification, so the SDF Annotator uses the defaults.
module top;
???
cpu m1(i1,i2,i3,o1,o2,o3);
fpu m2 (i4,o1,o3,i2,o4,o5,o6);
dma m3(o1,o4,i5,i6,i2);
// perform annotation
initial
begin
$sdf_annotate("cpu.sdf",m1,,"cpu.log");
$sdf_annotate("fpu.sdf",m2,,"fpu.log");
$sdf_annotate("dma.sdf",m3,,"dma.log");
end
// stimulus and response-checking
???
endmodule
Annotation with Arrays of Instances
This example shows arrays of instance in a design hierarchy. There is no configuration file
specification, so the SDF Annotator uses the defaults.
module top;
???
cpu ar[1](i1,i2,i3,o1,o2,o3);
fpu ar[2](i4,o1,o3,i2,o4,o5,o6);
dma ar[3](o1,o4,i5,i6,i2);
// perform annotation
initial
begin
$sdf_annotate("cpu.sdf",ar[1],,"cpu.log");
$sdf_annotate("fpu.sdf",ar[2],,"fpu.log");
$sdf_annotate("dma.sdf",ar[3],,"dma.log");
end
// stimulus and response-checking
???
endmodule

soelife

学习一下

zrzf23