一篇介绍Serdes和CDR以及PLL，VCO的非常详细的2008美国学位论文

shaolongliu.pku

强烈推荐，该论文一共分为九章，介绍非常详细，有基础，也有提升，最宝贵的是详细的系统级仿真验证方案，设计方案对比以及许多经验性的总结。



Abstract .............................................................................................................................. iii
List of Figures ................................................................................................................... vii
List of Tables ..................................................................................................................... xi
Chapter 1 ............................................................................................................................. 1
1 Introduction ................................................................................................................. 1
1.1 Introduction of Serial Link Systems ................................................................... 1
1.2 Goals and objectives ........................................................................................... 3
References ........................................................................................................................... 6
Chapter 2 ............................................................................................................................. 8
2 Modeling and Verification of High-Speed Wired Links with Verilog-AMS ............. 8
2.1 Introduction ......................................................................................................... 8
2.2 Input Signal Modeling ...................................................................................... 10
2.2.1 Clock with Jitter Modeling ........................................................................... 10
2.2.2 Data with Jitter Modeling ............................................................................. 12
2.3 System and Circuit Modeling ........................................................................... 13
2.3.1 System-Level Modeling ................................................................................ 13
2.3.2 Circuit Level Modeling ................................................................................. 14
2.4 Design Verification ........................................................................................... 14
2.4.1 Test Bench .................................................................................................... 15
2.4.2 Critical Path Detector .................................................................................... 15
2.4.3 System Level Verification ............................................................................ 16
2.5 Conclusions ....................................................................................................... 18
References ......................................................................................................................... 18
Chapter 3 ........................................................................................................................... 20
3 Accurate Prediction of Jitter Tolerance in High-Speed Serial Links ........................ 20
3.1 Introduction ....................................................................................................... 20
3.2 Jitter Tolerance Verification ............................................................................. 21
3.3 Simulation and Measurement ........................................................................... 27
3.4 Conclusions ....................................................................................................... 31
References ......................................................................................................................... 31
Chapter 4 ........................................................................................................................... 33
4 LC and Ring VCO PLL Design Comparison ........................................................... 33
4.1 Introduction ....................................................................................................... 33
4.2 PLL Architectures and Analysis ....................................................................... 35
4.2.1 VCO Topologies and Trade-off .................................................................... 37
4.2.2 Frequency, Power, and Area Analysis .......................................................... 44
4.2.3 Performance and Circuit Analysis ................................................................ 48
4.3 Simulation Comparison and Measured results ................................................. 53
4.4 Conclusion ........................................................................................................ 62
References ......................................................................................................................... 62
Chapter 5 ........................................................................................................................... 69
5 Programmable, Low Jitter Spread Spectrum Clock Generator with High EMI
Reduction .......................................................................................................................... 69
5.1 Introduction ....................................................................................................... 69
5.2 PLL based SSC Clock Generator architecture .................................................. 70
5.3 Design with Simulated and Measured Results.................................................. 73
5.4 Conclusions ....................................................................................................... 80
References ......................................................................................................................... 80
Chapter 6 ........................................................................................................................... 83
6 Simultaneous Bi-Directional PAM-4 Link with Built-In Self-Test .......................... 83
6.1 Introduction ....................................................................................................... 83
6.2 Architecture ....................................................................................................... 84
6.3 Simulation Results ............................................................................................ 88
6.4 Conclusions ....................................................................................................... 93
References ......................................................................................................................... 93
Chapter 7 ........................................................................................................................... 96
7 Architectures for Multi-Gigabit Wire-Linked Clock and Data Recovery ................ 96
7.1 Introduction ....................................................................................................... 96
7.2 CDR Architectures ............................................................................................ 99
7.2.1 PLL-based CDR .......................................................................................... 100
7.2.1.1 PLL based CDR Designs without Reference Clock ........................... 100
7.2.1.2 PLL-based CDR with an External Reference Clock........................... 102
7.2.1.3 Digital PLL (DPLL) based CDR Designs .......................................... 104
7.2.2 DLL-based CDR ......................................................................................... 106
7.2.3 Combination of PLL/DLL based CDR ....................................................... 107
7.2.4 Phase Interpolator (PI) based CDR ............................................................. 109
7.2.5 Injection Locked based CDR ...................................................................... 112
7.2.6 Oversampling based CDR........................................................................... 113
7.2.7 Gated Oscillator based CDR ....................................................................... 115
7.2.8 High-Q Filter based CDR ........................................................................... 116
7.3 Performance Comparison and Tradeoffs ........................................................ 117
7.4 Conclusions ..................................................................................................... 120
References ....................................................................................................................... 121
Chapter 8 ......................................................................................................................... 127
8 Clock and Data Recovery with Adaptive Loop Gain for Spread Spectrum SerDes
Applications .................................................................................................................... 127
8.1 Introduction ..................................................................................................... 127
vi
8.2 CDR Architecture ........................................................................................... 129
8.2.1 Phase Detector ............................................................................................ 130
8.2.2 Phase Interpolator ....................................................................................... 131
8.2.3 Frequency Differentiator ............................................................................. 132
8.2.4 Adaptive Loop Gain Filter .......................................................................... 133
8.3 Calculation and Simulation Results ................................................................ 135
8.4 Conclusion ...................................................................................................... 139
References ....................................................................................................................... 139
Chapter 9 ......................................................................................................................... 140
9 Conclusion and Future Work .................................................................................. 140
9.1 Single Chip Multi-Channel Serial Link .......................................................... 140
9.2 Research Summary and Future Work ............................................................. 146
References ....................................................................................................................... 147
Bibliography ................................................................................................................... 148

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