1 Ram and ROm are treated as black boxes
You don't have to do anything.
If you like to have high coverage, you have to build the wrapper for them to get good coveage.
2. X in STIL is normal, nothing wrong about that.
3. ATPG don't care the timing issue.
Without SDF, you have to make sure all combitional logic are 0 delay and have seqential cell with some delay to check the ATPG pattern.