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filter: process(clk, rst)
begin
if rst = '0' then
st <= s0;
fil_outQ(17 downto 0)<= (others =>'0');
elsif RISING_EDGE(clk) then
if fil_ready = '1' then
fil_cnt <= 0;
product_Q <= (others =>'0');
sum_Q <= (others =>'0');
fil_ramQ_rdaddr <= fil_ramQ_wraddr ;
signaltap_rom_addr <= (others =>'0');
st <= s1;
else null;
end if;
end if;
case st is
when s0 =>
signaltap_rom_addr <= (others =>'0');
fil_cnt <= 0;
product_Q <= (others =>'0');
sum_Q <= (others =>'0');
filter_out_ready <= '0';
when s1 =>
data_Q <= fil_ramQ_rddata;
data_stap <= signaltap_rom_data;
product_Q <= data_stap*data_Q;
sum_Q <= sum_Q +(product_Q(29)&product_Q);
fil_ramQ_rdaddr <= fil_ramQ_rdaddr - 1;
signaltap_rom_addr <= signaltap_rom_addr+1;
if fil_cnt = 253 then
fil_outQ(17 downto 0) <= sum_Q(29 downto 12)+("0000000000000000"&sum_Q(11));
fil_cnt<= fil_cnt + 1;
elsif fil_cnt = 254 then
filter_out_ready <= '1';
fil_cnt <= fil_cnt + 1;
elsif fil_cnt = 255 then
st <= s0;
filter_out_ready <= '0';
else
fil_cnt <= fil_cnt + 1;
filter_out_ready <= '0';
end if;
when others => st <= s0 ;
end case;
--else null;
--end if;
end process;
代码段在这里
但是就是有个 Error couldn't implement registers for assignments on this clock edge 在第六行 elsif RISING_EDGE(clk) then这里 我看到可能是elsif 后没有else了但是我改了还是出现这个问题···请高手指点一下··· |
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