A Low-Voltage High Performance CMOS pipelined ADC

hi_china59

A Low-Voltage High Performance CMOS pipelined Analog-to-Digital Converter

Chapter 1. Overview
1.0 Motivation 9
1.1 Technical Challenges and constraints 9
1.2 Project Goals and Deliverable 10
1.3 High Level Project Overview of the pipelined A/D converter 12
1.3.1 Sub-ADC 13
1.3.2 Multiplying DAC 13
1.3.3 Amplifier 14
1.3.4 Digital error correction 15
1.4 Project flow 17
1.4.1 Project decomposition: 17
1.4.2 Demonstration and Results of the project 18
1.4.3 Project Responsibilities: 18
1.4.4 Schedule of the project: 19
1.5 Report Overview 19
1.6 References 19

Chapter 2. Design on sub-ADC
2.0 Overview of sub-analog-to-digital converter (sub-ADC) 21
2.1 Design Realization 21
2.1.1 The Operation of the comparator 22
2.1.2 Design parameters consideration of the latch-type comparator 23
2.2 Testing Strategies of the comparator 24
2.2.1 The Specification and the comparison of the latch-type comparator 26
2.3 Offset Consideration of the latch-type comparator 27
2.3.1 Floorplan and Layout of the latch-type comparator 29
2.4 References 30

Chapter 3. Design on the Multiplying DAC (MDAC)
3.1 Overview on sub-DAC and Sample/Hold circuits 31
3.3 Complementary Switches versus Clock Boost Circuits 33
3.4 Architecture of the sub-DAC and Sample/Hold Circuit 34
3.5 Size of capacitor used 35
3.6 The pre-layout simulation on the sub-DAC and the S/H 36
3.6.1 Analog multiplexer 36
3.6.2 Charge injection error[1] 36
3.6.3 Charge injection, and gain error from real amplifier 39
3.7 Layout of the sub-DAC and the S/H circuit 41
3.7.1 Floorplan of the sub-DAC and the S/H circuit 41
3.7.2 Value of the extracted capacitor 42
3.7.3 The post-layout simulation of the analog multiplexer 43
3.8 References 43

Chapter 4. Design on the amplifier
4.0 Introduction 44
4.1 Design of the first 4 stages amplifier 44
4.2 Design Consideration in constructing the gain-boosting amplifier 46
4.3 Testing profile and Pre-Layout Simulation results 47
4.4 Floorplan, Layout, and post-layout simulation results 50
4.5 The overview of the amplifier utilized in the later stages 52
4.6 Design Considerations of the amplifiers used in the later stages 53
4.7 The specifications of the amplifier 54
4.8 The floorplan and the layout of the amplifier 58
4.9 References 58

Chapter 5. Design on the Digital Error Correction
5.0 Introduction 59
5.1 Design of the Digital Error Correction Circuit 59

Chapter 6. Amplifier sharing
6.0 Introduction 61
6.1 Operation of the technique 61

Chapter 7. Power Optimization
7.0 Introduction 63
7.1 System architecture of the pipelined ADC 63
7.2 pipelined with identical stage 64
7.3 Pipelined architecture with capacitor scaling 65
7.4 References 67

Chapter 8. The Whole pipelined A/D converter
8.0 Overview of a single stage 68
8.1 The testing method applied in a single stage of the ADC 68
8.2 Whole Pipelined A/D converter Architecture 69
8.3 System Requirements of the whole pipelined A/D converter 70
8.4 Clocking strategies in the whole pipelined A/D converter 71
8.5 Amplifier Sharing technique 71
8.6 Testing Profile of the whole circuit 71
8.7 The layout and the post-layout simulation of the whole circuit 79

Chapter 9. Further Works
9.0 Internal Clock Generator 81
9.1 Bandwidth and Capacitor Scalings 81
9.2 NMOS Switches with Clock Boost Circuits 81
9.3 Parallel-Pipeline Architecture 81
9.4 Different Number of Bits per stage 82

Chapter 10. Conclusion
10.0 General Conclusion 83

Chapter 11. Appendices
11.1 Design and Development 84
11.2 Detailed Derivation of ta for SPA, MSA and RSA. 86
11.3 Design Equations for the latch-type comparator 87
11.4 Offset voltage calculation of the latch-type comparator 91
11.5 Appendices on the amplifier 96
11.5.1 The detailed calculation of the device sizes in the amplifier 97
11.6 The schematic and the layout of each individual building blocks 99
11.6.1 The schematic and the layout of the comparators in the SADC 99
11.6.2 The schematic and the layout of the amplifiers 105
11.6.3 The schematic and the layout of the sub-DAC, the S/H 113
11.6.4 The schematic and the layout of the whole circuit 121
11.6.5 The schematic and the layout of the DEC circuit 123
11.7 Budget Report of the project 125
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pickpunk

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gemini06061978

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wallace60

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wallace60

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bulcas

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akira_lim

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ghx_123456

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Ryggeor

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erictien

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