【Springer 2010 新书】ESD Design for Analog Circuits

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Part 1 of Content:
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1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Analog andDigital inPrismofESDDesign . . . . . . . . . . . 1
1.2 ImportantDefinitions . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 ESDProtectionNetwork . . . . . . . . . . . . . . . . . . 4
1.2.2 ESDClamps . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.3 AbsoluteMaximumLimits andPulsedSOA . . . . . . . 7
1.2.4 ESD Pulse Specification . . . . . . . . . . . . . . . . . . 8
1.2.5 Breakdown and Instability . . . . . . . . . . . . . . . . . 9
DECIMMTM Simulation Examples for Introduction . . . . . . . . . . 14
2 Conductivity Modulation in Semiconductor Structures
Under Breakdown and Injection . . . . . . . . . . . . . . . . . . . 15
2.1 ImportantDefinitions andLimitations . . . . . . . . . . . . . . . 15
2.1.1 Basic Semiconductor Structures . . . . . . . . . . . . . . 15
2.1.2 Conductivity Modulation and Negative
Differential Resistance . . . . . . . . . . . . . . . . . . . 17
2.1.3 Spatial Current Instability, Filamentation, and
Suppression . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.4 Snapback Operation . . . . . . . . . . . . . . . . . . . . 20
2.1.5 Notes to theMethodology of Material Presentation
in This Chapter . . . . . . . . . . . . . . . . . . . . . . . 22
2.2 Avalanche Breakdown in Reverse-Biased p–n Structure . . . . . 23
2.2.1 Analytical Description of the Avalanche
Breakdown Phenomenon . . . . . . . . . . . . . . . . . 24
2.2.2 Numerical Analysis of the Avalanche Breakdown
in the p+–p–n+Structure . . . . . . . . . . . . . . . . . . 26
2.3 Double-Avalanche–Injection in p–i–n Structures . . . . . . . . . 30
2.3.1 AnAnalyticalDescription of theEffect . . . . . . . . . . 30
2.3.2 NumericalAnalysis for the p–i–nDiodeStructure . . . . 31
2.4 Avalanche–Injection in Si n+–n–n+DiodeStructure . . . . . . . 33
2.4.1 Analytical Approach . . . . . . . . . . . . . . . . . . . . 34
2.4.2 SimulationAnalysis . . . . . . . . . . . . . . . . . . . . 36
2.5 Conductivity Modulation Instability in n–p–n Diode Structures . 37
2.5.1 Conductivity Modulation in a Floating Base
RegioniodeOperationMode . . . . . . . . . . . . . . 37
2.6 Conductivity Modulation in the Triode n–p–n Structure . . . . . 40
2.6.1 The Case of Grounded Base Breakdown
Operation UEB=0(BVCES) . . . . . . . . . . . . . . . 40
2.6.2 The Floating Emitter Case IE =0 . . . . . . . . . . . . . 41
2.6.3 Avalanche–Injection in a Common Emitter
Circuit: The Case of IB<0Regime . . . . . . . . . . . . . 41
2.6.4 Avalanche–Injection in the Common Emitter
Circuit with Positive Base Current IB >0 . . . . . . . . . 47
2.6.5 Avalanche–Injection in the Common Base Circuit . . . . 51
2.7 Avalanche–Injection in PNP Structures . . . . . . . . . . . . . . 52
2.8 Double Injection in Si p–n–p–n Structures . . . . . . . . . . . . 53
2.8.1 EquivalentCircuit . . . . . . . . . . . . . . . . . . . . . 53
2.8.2 Simulation of Conductivity Modulation in
p–n–p–n Structures . . . . . . . . . . . . . . . . . . . . 56
2.9 Spatial Current Instability Phenomena in Semiconductor
Structures with Negative Differential Resistance . . . . . . . . . 59
2.9.1 Current Filamentation at Avalanche–Injection . . . . . . 60
2.9.2 Current Filamentation Effect in Double-
Avalanche–Injection Conductivity Modulation . . . . . . 63
2.9.3 Current Filamentation Effect in the Case of
Double Injection . . . . . . . . . . . . . . . . . . . . . . 66
2.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
DECIMMTM Simulation Examples for Chapter 2 . . . . . . . . . . . . 68
3 Standard and ESD Devices in Integrated Process Technologies . . 69
3.1 ESD Specifics in Integrated Process Technology . . . . . . . . . 70
3.1.1 Typical DGO CMOS Process with Extended
Voltage Components . . . . . . . . . . . . . . . . . . . . 70
3.1.2 ESD Specific for BCD and BiCMOS Integrated
Process Flow . . . . . . . . . . . . . . . . . . . . . . . . 83
3.2 SafeOperatingArea inESDPulseRegime . . . . . . . . . . . . 87
3.2.1 SOA and Current Instability Boundary in Reliability . . . 88
3.2.2 PulsedSOAforESDRegimes . . . . . . . . . . . . . . . 90
3.2.3 ESD SOA for Typical Devices in BCD Process . . . . . . 92
3.2.4 Instability Boundary and SOA for ESD devices . . . . . . 96
3.2.5 Physical Limitation of ESD Devices. Spatial
ThermalRunaway . . . . . . . . . . . . . . . . . . . . . 98
3.3 Low-VoltageESDDevices inCMOSProcesses . . . . . . . . . 102
3.3.1 Snapback NMOS . . . . . . . . . . . . . . . . . . . . . 103
3.3.2 FOX(TFO)ESDdevice . . . . . . . . . . . . . . . . . . 105
3.3.3 LVTSCRandFOXSCR . . . . . . . . . . . . . . . . . . 109
3.3.4 Low-Voltage Avalanche Diodes . . . . . . . . . . . . . . 111
3.4 ESDDevices inBJTProcesses . . . . . . . . . . . . . . . . . . 114
3.4.1 IntegratedNPNBJTDevices . . . . . . . . . . . . . . . 114
3.4.2 BipolarSCR . . . . . . . . . . . . . . . . . . . . . . . . 116
3.5 High-Voltage ESD Devices in BCD and Extended
VoltageCMOSProcesses . . . . . . . . . . . . . . . . . . . . . 117
3.5.1 LDMOS-SCRandDeMOS-SCRDevices . . . . . . . . . 118
3.5.2 LateralPNPBJTDevices . . . . . . . . . . . . . . . . . 121
3.5.3 High-Voltage Avalanche Diodes . . . . . . . . . . . . . . 126
3.6 DualDirectionDevices . . . . . . . . . . . . . . . . . . . . . . 127
3.6.1 Dual-Direction Device Architecture in CMOS Process . . 128
3.6.2 High-VoltageDual-DirectionDevices . . . . . . . . . . . 131
3.6.3 Dual Direction ESD Devices Based upon Si–Ge
NPNBJTStructure . . . . . . . . . . . . . . . . . . . . 134
3.7 ESD Diodes and Passive Components . . . . . . . . . . . . . . . 139
3.7.1 Forward-Biased ESD Diodes . . . . . . . . . . . . . . . 139
3.7.2 Passives . . . . . . . . . . . . . . . . . . . . . . . . . . 142
3.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
DECIMMTM Simulation Examples for Chapter 3 . . . . . . . . . . . . 148
4 ESD Clamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.1 ActiveNMOSClamp . . . . . . . . . . . . . . . . . . . . . . . 158
4.2 Low-Voltage Clamps with Internal Blocking Junction
Reference or dV/dtTurn-on . . . . . . . . . . . . . . . . . . . . 161
4.2.1 Snapback NMOS Clamps . . . . . . . . . . . . . . . . . 161
4.2.2 Transient-Triggered PMOS Clamp . . . . . . . . . . . . 167
4.2.3 10 V FOX Snapback Device . . . . . . . . . . . . . . . . 169
4.2.4 LVTSCRandFOX-SCRClamps . . . . . . . . . . . . . 171
4.2.5 HighHoldingVoltageLVTSCRClamps . . . . . . . . . 172
4.2.6 Triggering Characteristics Control in SCR Clamps . . . . 176
4.3 Voltage and Current Reference in ESD Clamp . . . . . . . . . . 182
4.3.1 Low-Voltage Clamps in BiCMOS process technology . . 183
4.3.2 NPN Clamps with Voltage Reference . . . . . . . . . . . 185
4.4 High-VoltageESDDevices . . . . . . . . . . . . . . . . . . . . 188
4.4.1 20 V NPN with Blocking Junction Internal Reference . . 189
4.4.2 NPN Clamp with External Lateral Avalanche
Diode Reference . . . . . . . . . . . . . . . . . . . . . . 190
4.4.3 SCR-BasedHigh-VoltageClamp . . . . . . . . . . . . . 190
4.4.4 LateralLPNPClamp . . . . . . . . . . . . . . . . . . . . 190
4.4.5 MixedDevice-CircuitDualModeSolutions . . . . . . . 191
4.5 The Concept of Self-Protection . . . . . . . . . . . . . . . . . . 196
4.5.1 Device-LevelSelf-Protection . . . . . . . . . . . . . . . 196
4.5.2 Array-LevelProtection . . . . . . . . . . . . . . . . . . 198
4.6 ESDProtection ofUltraHighVoltageCircuits . . . . . . . . . . 200
4.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
DECIMMTM Simulation Examples for Chapter 4 . . . . . . . . . . . . 204

mscyc0909

Part 2 of Content:
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5 ESD Network Design Principles . . . . . . . . . . . . . . . . . . . . 213
5.1 Rail-BasedESDProtectionNetwork . . . . . . . . . . . . . . . 215
5.1.1 Rail Based and Local ESD Protection . . . . . . . . . . . 215
5.1.2 Rail-Based ESD Protection Using Snapback Clamps . . . 217
5.1.3 Rail-BasedESDProtectionUsingActiveClamps . . . . 219
5.1.4 Specific of Active Clamp Design in BiCMOS Processes . 223
5.1.5 Bipolar Differential Input Protection . . . . . . . . . . . 232
5.1.6 BipolarOutputProtection . . . . . . . . . . . . . . . . . 234
5.1.7 CMOS Input and Output Protection . . . . . . . . . . . . 235
5.1.8 Array-LevelConsideration . . . . . . . . . . . . . . . . 237
5.1.9 Concept of Two-Stage Protection . . . . . . . . . . . . . 240
5.2 Local Clamp-Based ESD Protection Network . . . . . . . . . . . 247
5.2.1 Local ESD Protection . . . . . . . . . . . . . . . . . . . 247
5.2.2 SerialDataLinePinCaseStudy . . . . . . . . . . . . . . 248
5.2.3 ErasePinProtection inEEPROM . . . . . . . . . . . . . 250
5.2.4 Local Protection of the Internal Pins . . . . . . . . . . . 253
5.2.5 Local Protection of the High-Speed I/O pins . . . . . . . 256
5.3 ESD Network for Multiple Voltage Domains . . . . . . . . . . . 258
5.3.1 Multiple Voltage Domains . . . . . . . . . . . . . . . . . 258
5.3.2 Protection of Multiple Voltage Domains with
SingleActiveClampNetwork . . . . . . . . . . . . . . . 260
5.3.3 Local Bi-directional ESD Protection of
Differential Input . . . . . . . . . . . . . . . . . . . . . 261
5.4 ESD Network Simulation with ESD Compact Models . . . . . . 263
5.4.1 Compact Model for Snapback NMOS and PMOS
Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
5.4.2 Snapback LVTSCR Model . . . . . . . . . . . . . . . . . 265
5.4.3 Extended Voltage Snapback Compact Models . . . . . . 265
5.4.4 High-VoltageOpenDrainCircuitAnalysis . . . . . . . . 270
5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
DECIMMTM Simulation Examples for Chapter 5 . . . . . . . . . . . . 272
6 ESD Design for Signal Path Analog . . . . . . . . . . . . . . . . . . 281
6.1 Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
6.1.1 Amplifier Product Families and Specifications . . . . . . 282
6.1.2 ESDSolutions forAmplifiers . . . . . . . . . . . . . . . 288
6.1.3 BipolarOutputHigh-VoltageAudioAmplifiers . . . . . . 290
6.1.4 Bipolar Output Protection in Low-Voltage Amplifiers . . 292
6.1.5 Input Protection . . . . . . . . . . . . . . . . . . . . . . 293
6.1.6 CMOSOutput . . . . . . . . . . . . . . . . . . . . . . . 295
6.2 Digital-to-Analog andAnalog-to-DigitalConverters . . . . . . . 296
6.2.1 Functional Blocks for High-Speed DAC . . . . . . . . . 297
6.3 High-Speed Interface IO pins . . . . . . . . . . . . . . . . . . . 301
6.3.1 Interface Analog Products . . . . . . . . . . . . . . . . . 301
6.3.2 Cable Discharge Event Test Procedure for
IntegratedCircuits . . . . . . . . . . . . . . . . . . . . . 302
6.3.3 ESD Protection of Interface Pins with CDE
Requirements . . . . . . . . . . . . . . . . . . . . . . . 305
6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
DECIMMTM Simulation Examples for Chapter 6 . . . . . . . . . . . . 307
7 Power Management Circuits’ ESD Protection . . . . . . . . . . . . 317
7.1 Power Management Products . . . . . . . . . . . . . . . . . . . 318
7.1.1 Power Management Products and ESD Challenges . . . . 318
7.1.2 IntegratedDC–DCConverters andControllers . . . . . . 321
7.1.3 IntegratedPowerArrays . . . . . . . . . . . . . . . . . . 323
7.2 Low-VoltagePowerCircuitESDCases . . . . . . . . . . . . . . 338
7.2.1 LV Power Switching Blocks . . . . . . . . . . . . . . . . 338
7.2.2 Step-DownDC–DCConverters . . . . . . . . . . . . . . 340
7.2.3 Local Snapback Protection of LV Switch Pin . . . . . . . 343
7.3 ESDProtection of IntegratedHigh-VoltageRegulators . . . . . . 347
7.3.1 Asynchronous Integrated Buck Regulator Case . . . . . . 347
7.3.2 Synchronous Regulators . . . . . . . . . . . . . . . . . . 351
7.4 Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
7.4.1 Asynchronous Buck-Boost (SEPIC) Controller . . . . . . 359
7.4.2 Synchronous Buck Controller . . . . . . . . . . . . . . . 362
7.5 Light Management Units and LED Drivers . . . . . . . . . . . . 364
7.5.1 Analog LED Technology . . . . . . . . . . . . . . . . . 364
7.5.2 LEDDrivers . . . . . . . . . . . . . . . . . . . . . . . . 366
7.5.3 Light Management Units . . . . . . . . . . . . . . . . . 367
7.6 AFewMoreCaseStudies . . . . . . . . . . . . . . . . . . . . . 374
7.6.1 Power Array–ESD Clamp Interaction . . . . . . . . . . . 374
7.6.2 Nepi–Nepi Transient Latch-Up Scenario . . . . . . . . . 377
7.6.3 CDMCase of theHigh-VoltagePinProtection . . . . . . 380
7.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
DECIMMTM Simulation Examples for Chapter 7 . . . . . . . . . . . . 387
8 System-Level and Discrete Components ESD . . . . . . . . . . . . 395
8.1 System-Level Specifications and Standards . . . . . . . . . . . . 396
8.1.1 Meaning of ESD Robust System . . . . . . . . . . . . . 396
8.1.2 System-Level ESD Pulse and Model . . . . . . . . . . . 400
8.1.3 TransientLatch-upDuringaSystem-LevelEvent . . . . . 405
8.1.4 System-Level Protection Components . . . . . . . . . . . 408
8.2 On-Wafer Human Metal Model Measurements . . . . . . . . . . 409
8.2.1 On-Wafer HMM Tester and Equivalent Circuit of
thePulse . . . . . . . . . . . . . . . . . . . . . . . . . . 410
8.2.2 HMM-HBM Component Correlation . . . . . . . . . . . 412
8.3 On-ChipDesign forSystem-LevelPins . . . . . . . . . . . . . . 416
8.3.1 Examples of Circuits with System-Level Protection . . . 416
8.4 HotSwap andHotPlug-in . . . . . . . . . . . . . . . . . . . . . 422
8.4.1 The Concept of Two-Stage SCR ESD Devices . . . . . . 422
8.5 System-on-Package (SOP) Protection . . . . . . . . . . . . . . . 428
8.6 ESD Robustness of Discrete Components . . . . . . . . . . . . . 429
8.6.1 Discrete Components in High Reliability Systems . . . . 429
8.6.2 ESD Requirement for Discrete Components . . . . . . . 429
8.6.3 Preliminary Numerical Analysis for Devices with
Defects and the Two-Transistor Model . . . . . . . . . . 432
8.6.4 Experimental Evaluation of Discrete Components
Robustness . . . . . . . . . . . . . . . . . . . . . . . . . 436
8.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
DECIMMTM Simulation Examples for Chapter 8 . . . . . . . . . . . . 443
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

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