关于FPGA实现PCI initiator的问题

wcb5658

我用xilinx的PCI core，实现PCI initiator,想往计算机内存中快速导数据。

出现的问题：FPGA发出了REQ_N信号，仲裁器也响应了GNT_N信号，但是DEVSEL_N和TRDY_N信号一致无效。请问是什么原因？

注：FPGA要传送的目标地址为计算机内存中开辟一个数组的起始地址，本例中为0x0042C3A0(4375456)；

wcb5658

Set core to initiator mode and start state-mechine,but the DEVSEL_N,TRDY_N signals inactive always.
1.PC open device;
2.Set PCI command's 0x0007;
3.reset the initiator controler;
4.PC request a memory space(a array) and send the address to FPGA's Target_Addr;
5.the burst lenth is the constant value in code;
6.PC start state-mechine for initiator write;
7.the AD[31:0],CBE[3:0],FRAME_N,IRDY_N,REQ_N signals is phase normal,but the GNT_N,DEVSEL_N,TRDY_N signals phase error.
8.GNT_N is inserted when REQ_N active,but the GNT_N keep low-level whenever REQ_N inactive.
9.the DEVSEL_N,TRDY_N signals keep inactive all the time at initator state.
10.modify code in XPCI_USER file:
always @(posedge CLK or posedge RST)
begin : edge_detect
        if (RST) M_DATAQ = 1'b0;
        else M_DATAQ = M_DATA;
end
assign M_DATA_FELL = !M_DATA & M_DATAQ; //falling-edge detect
always @(posedge CLK or posedge Rst_Initor_St)
begin : watch_statu
        if (Rst_Initor_St)
                begin
                        FATAL <= 1'b0;
                        RETRY <= 1'b0;
                end
        else if (!M_ADDR_N)// clear at beginning
                begin
                        FATAL <= 1'b0;
                        RETRY <= 1'b0;
                end
        else if (M_DATA)// latch until end
                begin
                        FATAL <= CSR[39] | CSR[38];
                        RETRY <= CSR[36];
                end
end
always @(posedge CLK or posedge Rst_Initor_St) begin : initiator_fsm
        if ( Rst_Initor_St ) begin
                STATE <= IDLE_S;
                FatalErr <= 1'b0;
        end else case (STATE)
                IDLE_S :begin
                        if ( START_FG ) STATE <= REQ_S;
                        else STATE <= IDLE_S;
                end               
                REQ_S :        STATE <= WRITE_S;                       
                WRITE_S :        if (M_DATA_FELL) begin       
                                if (FATAL)
                                        STATE <= DEAD_S;
                                else if (RETRY)
                                        STATE <= RETRY_S;
                                else
                                        STATE <= DONE_S;
                        end                       
                RETRY_S :        STATE <= REQ_S;                       
                DONE_S : STATE <= IDLE_S;                       
                DEAD_S : begin
                        STATE <= DEAD_S;
                        FatalErr <= 1'b1;
                end
                default :        STATE <= IDLE_S;
                endcase
end
always @(posedge CLK or posedge RST)
begin
        if (RST) begin
           M_READY <= 1'b0;
                M_WRDN  <= 1'b0;
        end else begin
           M_READY <= SynSTART;
                M_WRDN  <= START;
   end
end
always @(posedge CLK or posedge Rst_Initor_St)
begin : transfer_counter
        if (Rst_Initor_St) XFER_CNT <= 9'h0;
        else if (START_FG) XFER_CNT <= 9'h00F; //burst length
        else if ( Fifo_RdReq )XFER_CNT <= XFER_CNT - 1;
end
always @(posedge CLK or posedge Rst_Initor_St)
begin : driving_complete
        if (Rst_Initor_St)         COMPLETE_reg <= 1'b0;
        else if (START_FG) COMPLETE_reg <= 1'b0;
                else if(XFER_CNT == 9'h1) COMPLETE_reg <= 1'b1;
end
assign REQUEST = (STATE == REQ_S);
assign REQUESTHOLD = 1'b0;
assign COMPLETE    = COMPLETE_reg;
assign bar0_dout   = M_ADDR_N ? Fifo_Out : Target_Addr;
assign M_CBE       = M_ADDR_N ? 4'b0000  : 4'b0111;
assign Fifo_RdReq  = M_SRC_EN & M_DATA;