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[Paper]A High-Efficiency CMOS +22-dBm Linear Power Amplifier

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发表于 2006-9-19 15:37:39 | 显示全部楼层 |阅读模式

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Abstract—Modern wireless communication systems require power amplifiers with high efficiency and high linearity. CMOS is the technology of choice for complete systems on a chip due to its lower costs and high integration levels. However, it has always been difficult to integrate high-efficiency power amplifiers in CMOS. In this paper, we present a new class of operation (parallel A&B) for power amplifiers that improves both their dynamic range and power efficiency. A prototype design of the new amplifier was fabricated in a 0.18- m CMOS technology. Measurement results show a PAE that is over 44% and the measured output power is +22 dBm. In comparison to a normal class A amplifier, this new design increases the 1-dB compression point (P1dB) by over 3 dB and reduces dc power consumption by over 50% within the linear operating range.

Index Terms—Class A, class AB, CMOS, power amplifier.

A high-efficiency CMOS +22-dBm linear power amplifier.pdf

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发表于 2006-9-19 21:59:18 | 显示全部楼层
Thanks!!
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 楼主| 发表于 2006-9-21 11:57:10 | 显示全部楼层
为什么IEEE上的paper没有人来下呢,很纳闷啊!
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发表于 2007-1-21 22:36:02 | 显示全部楼层
haodongxi a ,xiexie le
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发表于 2007-1-22 10:48:01 | 显示全部楼层
REFERENCES
[1] D. Su and W. McFarland, “A 2.5-V, 1-W monolithic CMOS RF power
amplifier,” in Proc. IEEE Custom Integrated Circuits Conf., 1997, pp.
189–192.
[2] D. K. Su and W. J. McFarland, “An IC for linearizing RF power ampli-
fiers using envelope elimination and restoration,” IEEE J. of Solid-State
Circuits, vol. 33, no. 12, pp. 2252–2258, Dec. 1998.
[3] B. Baliweber, R. Gupta, and D. J. Allstot, “Fully-integrated CMOS
RF amplifier,” in Proc. IEEE Int. Solid-State Circuits Conf., 1999, pp.
72–73.
[19] IEEE Standard 802.11a-1999, Part 11: Wireless LAN Medium Access
Control (MAC) and Physical Layer (PHY) Specifications, High-Speed
Physical Layer in the 5 GHz Band (1999). [Online]. Available:
www.ieee.org
[20] C. Wang, M. Vaidyanathan, and L. E. Larson, “A capacitance-compensation
technique for improved linearity in CMOS class-AB power amplifiers,”
IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1927–1937,
Nov. 2004.
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发表于 2007-1-22 10:48:58 | 显示全部楼层

CONCLUSION

CONCLUSION
In this paper, we have presented a design for a new PA with a
parallel class A&B structure. This new amplifier provides superior
performance in terms of both linearity and power efficiency
in comparison to previous designs. Measurement results shows
a 12-dB power gain (single stage), 22-dBm output power, and
more than 44% PAE. More importantly, this circuit uses signifi-
cantly lower dc power at 4–8 dB back-off in comparison to other
class AB amplifiers.
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头像被屏蔽
发表于 2008-3-18 09:27:46 | 显示全部楼层
提示: 作者被禁止或删除 内容自动屏蔽
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发表于 2008-5-13 10:21:38 | 显示全部楼层
thanks
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发表于 2008-5-13 12:28:30 | 显示全部楼层
不错哈!谢谢了!
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发表于 2008-5-13 16:38:27 | 显示全部楼层
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