倍增电容LDO设计

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给大家上传一个新颖倍增电容LDO设计资料，很不错的。在此并给出它的英文摘要。感觉对您有用的，你就选择下载。
This paper presents a low quiescent current, highly stable low-drop out (LDO) regulator. In order to reduce capacitor value and control frequency response peak, capacitor multipliers are adopted in the compensation circuit with mathematic calculations. The phase margin is adequate when the load current is 0.1 or 150 mA. Fabricated in an XFAB 0.6 μ m CMOS process, the LDO produces 12.2 mV (0.7%) overshoot voltage while the current changes at 770 mA/100 μ s with a capacitor load of 10 μ F.

wangwang1

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leonken458

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hzfeiyun

Design of an LDO with capacitor multiplier

sjxu007

thanks

katherinezhang

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gemini06061978

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kuoyu2006

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yuqiumax

Vol. 31, No. 7 Journal of Semiconductors July 2010
Design of an LDO with capacitor multiplier
Ying Jianhua(应建华), Huang Meng(黄萌)
Ž, and Huang Yang(黄杨)
(Department of Electronic Science & Technology, Huazhong University of Science & Technology, Wuhan 430074, China)
Abstract: This paper presents a low quiescent current, highly stable low-drop out (LDO) regulator. In order to reduce
capacitor value and control frequency response peak, capacitor multipliers are adopted in the compensation circuit with
mathematic calculations. The phase margin is adequate when the load current is 0.1 or 150 mA. Fabricated in an XFAB
0.6 m CMOS process, the LDO produces 12.2 mV (0.7%) overshoot voltage while the current changes at 770 mA/100
s with a capacitor load of 10 F.

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