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Cadence Encounter Conformal Support:
1. Introduction
1.1 Formal verification versus simulation
1.2 Formal verification: what you need know
2. Formal Verification Design Flow
2.1 Quartus II integrated synthesis
2.2 EDA tool support for quartus II integrated synthesis
2.3 Synplify Pro
2.4 EDA tool supoort for synplify pro
3. RTL coding guidelines for quartus II integrated synthesis
3.1 synthesis directives and attributes
3.2 stuck-at registers
3.3 ROM, LPM_DIVIDE, and shift register inference
3.4 RAM interface
3.5 Latch interface
3.6 Combiantional loops
3.7 Finite state machine coding styles
4. Black boxes in the encounter conformal flow
4.1 TCL command
4.2 GUI
5. Generating the post-fit netlist output and the encounter conformal setup files
5.1 the quartus II software generated files, formal verification scripts and directories
6. Understanding the formal verification scripts for encounter conformal
6.1 the encounter conformal commands within the quartus II software-generated scripts
7. Comparing design using encounter conformal
7.1 running the encounter conformal software from the gui
7.2 runnign the encounter conformal software from a system command prompt |
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