Metamodeling-Driven_IP_Reuse_for_SoC_Integration_and_Microprocessor_Design

processor · 发表于 2010-6-19 17:07:19

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Metamodeling-Driven_IP_Reuse_for_SoC_Integration_and_Microprocessor_Design
国外09年的新书，新版的这个界面，我竟然不会发封皮的图片，真是Out了~
下面是书的目录，可以去amazon查看书的内容~

Preface xi
Acknowledgments xxi
Chapter 1 Introduction 1
1.1 Ongoing Efforts in Design IP Reuse 5
1.2 Ongoing Efforts in Verification IP Reuse 8
1.3 Essential Issues with IP Reuse 9
1.4 Metamodeling Approach to Reuse 13
1.5 Problem Statement 15
1.6 Research Contributions 17
1.7 Tools and Techniques Developed 18
References 19
Chapter 2 Background 23
2.1 Metamodeling 23
2.1.1 Implicit Metamodeling Versus Explicit Metamodeling 25
2.1.2 Generic Modeling Environment 26
2.2 Component Composition Framework 28
2.3 Reflection and Introspection (R-I) 30
2.4 SystemC 31
2.5 Model-Driven Validation 32
2.5.1 Microprocessor Validation Flow 32
2.5.2 Simulation-Based Functional Validation 35
2.6 Test Generation
2.6.1 Constraint Programming 36
2.6.2 Esterel Studio 37
2.7 Coverage-Directed Test Generation 38
2.7.1 Structural Coverage 38
2.7.2 Functional Coverage 40
2.7.3 Property Specification Language (PSL) 41
2.7.4 Fault Classification 41
References 42
Chapter 3 Related Work 45
3.1 Component Composition Framework 45
3.1.1 The BALBOA Framework 45
3.1.2 Liberty Simulation Environment (LSE) 46
3.1.3 EWD 47
3.1.4 Ptolemy II 47
3.1.5 Metropolis 48
3.2 Component-Based Software Design Environments 49
3.3 IP Interfacing Standards 50
3.3.1 SPIRIT 51
3.4 Existing Tools for Structural Reflection 51
3.5 Architecture Description Languages 53
3.6 Test Generation 54
References 56
I Design Reuse 61
Chapter 4 A Metamodel for Component Composition 63
4.1 CC Language, Metamodel, and Model 65
4.1.1 Component Composition Language (CCL) 65
4.1.2 Component Composition Metamodel (CCMM) 68
4.1.3 Component Composition Model (CCM) 77
4.2 CC Analysis and Translation 82
4.2.1 Consistency Checking 82
4.2.2 Type Inference 83
4.2.3 XML Translation 93
4.3 Case Studies 94
4.3.1 AMBA AHB RTL Bus Model 94
4.3.2 Simple Bus TL Model
4.4 Design Experience and Summary 100
References 101
Chapter 5 IP Reflection and Selection 103
5.1 Metadata for IP Composition 104
5.2 Metadata on a SystemC IP Specification 105
5.3 Tools and Methodology 113
5.3.1 Stage 1: SystemC Parsing 114
5.3.2 Stage 2: AST Parsing and DOM Population 114
5.3.3 Stage 3: Processing and Constraining DOM 118
5.4 IP Selection 123
5.4.1 Illustrative Example 130
5.5 Case Study 131
5.6 Summary 134
References 135
Chapter 6 Typing Problems in IP Composition 137
6.1 MCF Type Definitions 138
6.1.1 Component Composition Language 139
6.1.2 IP Library 144
6.2 Type Resolution in MCF 145
6.2.1 Type Inference on Architectural Template 146
6.2.2 Type Substitution Using IP Library 149
6.3 Comparative Study 156
6.4 Case Study 157
6.5 Summary 161
References 161
Chapter 7 IP Composition 163
7.1 MCF Ingredients 166
7.2 Handling Generic IPs 168
7.3 Interaction Pattern 170
7.3.1 Interaction Console 172
7.4 Case Study 174
7.5 Summary 178
References 178
Chapter 8 Checker Generation for IP Verification 181
8.1 Enhanced Design Flow
8.2 Enhanced Modeling Framework 183
8.2.1 Component Properties 185
8.2.2 Composition Properties 185
8.2.3 XML Translation 186
8.3 Interaction Console 187
8.4 Conclusion 191
References 191
II Verification Reuse 193
Chapter 9 A Metamodel for Microprocessors 195
9.1 Modeling and Validation Environment (MMV) 195
9.1.1 System-Level View (SV) 197
9.1.2 Architecture View (AV) 201
9.1.3 Microarchitecture View (MV) 207
9.2 Simulator Generation 212
9.2.1 Metamodel Additions for Simulator Generation 213
9.2.2 ALGS Generation 214
9.3 Test Generation 221
9.3.1 CSP Formulation for Generating Random Test Cases 221
9.4 Case Study: Modeling Vespa in MMV 224
9.4.1 System-Level Model 225
9.4.2 Architecture Model 228
9.4.3 Refinement of Real-Time Software Scheduler 230
9.4.4 Microarchitecture Model 232
9.5 Summary 234
References 235
Chapter 10 Design Fault Directed Test Generation 237
10.1 Motivation 238
10.2 Modeling and Test Generation 240
10.2.1 Architecture Modeling 240
10.2.2 Microarchitecture Modeling 240
10.2.3 CSP Formulation 242
10.2.4 Test Case Generator (TCG) 244
10.2.5 Usage Mode 245
10.3 Coverage Constraints 246
10.3.1 Statement Coverage
10.3.2 Branch Coverage 247
10.3.3 MCDC 248
10.3.4 Design Fault Coverage 249
10.4 Results 251
10.5 Summary 252
References 253
Chapter 11 Model-Driven System-Level Validation 255
11.1 Test Generation Methodology 256
11.1.1 Modeling and Simulation and Verification 256
11.1.2 Coverage Annotation 261
11.1.3 Test Generation 264
11.2 SystemC Validation 266
11.2.1 TestSpec Generator (TSG) 268
11.3 Case Study 269
11.3.1 PSM Specification 269
11.3.2 Functional Model 271
11.3.3 Verification Model 271
11.3.4 Coverage Annotation 271
11.3.5 Test Generation 272
11.3.6 Implementation Model 272
11.4 Summary 273
References 273
Chapter 12 Conclusion and Future Work 275
12.1 Summary 275
12.2 Future Work 278
12.2.1 Solution Methodology Enhancements 278
12.2.2 Extensions for Industry Recognition 279
References 281
About the Authors 285
Index

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