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Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver
Brian P. Ginsburg, Student Member, IEEE, and Anantha P. Chandrakasan, Fellow, IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 2, FEBRUARY 2007
Abstract—Ultra-wideband radio requires Nyquist sampling
rates of at least 500 MS/s with low resolutions. While flash is the
traditional choice for these specifications, a comparative energy
model is used to show the potential energy savings of the time-interleaved
successive approximation register architecture, which
requires only a linear number of comparisons versus exponential
for flash. A dual 500-MS/s, 5-bit ADC chip is implemented in a
0.18- m CMOS process, with both ADCs synchronized for use in
an I/Q UWB receiver. Each ADC uses a 6-way time-interleaved
SAR topology with full custom logic, self-timed bit-cycling, and
duty cycling of the comparator preamplifiers to enable 500-MS/s
operation with 7.8mWpower consumption. The output resolution
is adjustable down to the 1-bit level for additional power savings. |
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发表于 2010-6-16 09:56:47
