The need to have Transaction Level models early in the
design cycle is becoming more and more important to
shorten the development times of complex Systems-on-
Chip (SoC). These models need to be functional and
timing accurate in order to address different design usecases
during the SoC development. However the typical
issue with Transaction Level Modeling (TLM) techniques
is the accuracy vs. simulation speed trade-off. Most
models that have a high degree of time accuracy
(approaching RTL) are inherently slow due to clock
sensitive processes. Similarly, models that can run at high
simulation speeds are often modeled at abstraction levels
that make them unsuitable for detailed architecture
exploration or performance verification. This paper
introduces a new methodology that enables the creation of
fast and cycle accurate protocol specific bus-based
communication models, based on the new TLM 2.0
standard from the Open SystemC Initiative (OSCI).
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发表于 2010-6-4 17:10:42
发表于 2010-6-4 23:44:05
