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1.24-Bit 5.0 GHz Direct Digital Synthesizer RFIC With Direct Digital Modulations in 0.13 m SiGe BiCMOS Technology
2.A 300–800 MHz Tunable Filter and Linearized LNA Applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver
3.Linearized Dual-Band Power Amplifiers With Integrated Baluns in 65 nm CMOS for a 2 2 802.11n MIMO WLAN SoC
4.The Experimental Demonstration of a SASP-Based Full Software Radio Receiver
5.An Active Feedback Interference Cancellation Technique for Blocker Filtering in RF Receiver Front-Ends
6.Effect of Substrate Contact Shape and Placement on RF Characteristics of 45 nm Low Power CMOS Devices
7.A 10-bit Charge Redistribution ADC Consuming 1.9 W at 1 MS s
8.A Low-Power Capacitive Charge Pump Based Pipelined ADC
9.An Amorphous-Silicon Operational Amplifier and Its Application to a 4-Bit Digital-to-Analog Converter
10.A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop
11.A 1.27 GHz, All-Digital Spread Spectrum Clock Generato Synthesizer in 65 nm CMOS
12.A Low THD, Low Power, High Output-Swing Time-Mode-Based Tunable Oscillator Via Digital Harmonic-Cancellation Technique
13.Multi-Level Amplitude Modulation of a 16.8-GHz Class-E Power Amplifier With Negative Resistance Enhanced Power Gain for 400-Mbps Data Transmission
14.Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs |
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发表于 2010-5-31 16:07:52
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