Verilog-AMS Language Reference Manual（V2.2）

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    Table of Contents

1 Verilog-AMS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 Overview 1
1.2 Mixed-signal language features 2
1.3 Systems 3
1.3.1 Conservative systems 4
1.3.2 Kirchhoff’s Laws 5
1.3.3 Natures, disciplines, and nets 6
1.3.4 Signal-flow systems 6
1.3.5 Mixed conservative/signal flow systems 7
1.4 Conventions used in this document 10
1.5 Contents 11

2 Lexical conventions . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1 Lexical tokens 13
2.2 White space 13
2.3 Comments 14
2.4 Operators 14
2.5 Numbers 14
2.5.1 Integer constants 15
2.5.2 Real constants 15
2.5.3 Scale factors for real constants 16
2.6 Strings 17
2.6.1 String variable declaration 17
2.6.2 String manipulation 17
2.6.3 Special characters in strings 18
2.7 Identifiers, keywords, and system names 18
2.7.1 Escaped identifiers 19
2.7.2 Keywords 19
2.7.3 System tasks and functions 19
2.7.4 Compiler directives 20
2.8 Attributes 20
2.8.1 Standard attributes 21

3 Data types . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.1 Integer and real data types 23
3.1.1 Output variables 24
3.2 Parameters 25
3.2.1 Type specification 27
3.2.2 Value range specification 27
3.2.3 Parameter units and descriptions 28
3.2.4 Parameter arrays 29
3.2.5 Local parameters 29
3.2.6 String parameters 30
3.2.7 Parameter aliases 30
3.3 Genvars 31
3.4 Net_discipline 32
3.4.1 Natures 33
3.4.2 Disciplines 36
3.4.3 Net discipline declaration 41
3.4.4 Ground declaration 43
3.4.5 Implicit nets 44
3.5 Real net declarations 44
3.6 Default discipline 45
3.6.1 Disciplines of primitives 45
3.7 Discipline precedence 46
3.8 Net compatibility 47
3.8.1 Discipline and Nature Compatibility 47
3.9 Branches 49
3.10 Namespace 50
3.10.1 Nature and discipline 50
3.10.2 Access functions 51
3.10.3 Net 51
3.10.4 Branch 51

4 Expressions . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.1 Operators 53
4.1.1 Operators with real operands 54
4.1.2 Binary operator precedence 55
4.1.3 Expression evaluation order 56
4.1.4 Arithmetic operators 56
4.1.5 Relational operators 57
4.1.6 Case equality operators 58
4.1.7 Logical equality operators 58
4.1.8 Logical operators 58
4.1.9 Bit-wise operators 59
4.1.10 Shift operators 60
4.1.11 Conditional operator 60
4.1.12 Event or 60
4.1.13 Concatenations 60
4.2 Built-in mathematical functions 61
4.2.1 Standard mathematical functions 61
4.2.2 Transcendental functions 62
4.2.3 Error handling 63
4.3 Signal access functions 63
4.4 Analog operators 64
4.4.1 Restrictions on analog operators 64
4.4.2 Vector or array arguments to analog operators 65
4.4.3 Analog operators and equations 65
4.4.4 Time derivative operator 65
4.4.5 Time integral operator 66
4.4.6 Circular integrator operator 67
4.4.7 Derivative operator 68
4.4.8 Absolute delay operator 70
4.4.9 Transition filter 71
4.4.10 Slew filter 75
4.4.11 last_crossing function 76
4.4.12 Laplace transform filters 77
4.4.13 Z-transform filters 79
4.4.14 Limited exponential 82
4.4.15 Constant versus dynamic arguments 83
4.5 Analysis dependent functions 84
4.5.1 Analysis 84
4.5.2 DC analysis 85
4.5.3 AC stimulus 86
4.5.4 Noise 86
4.6 User-defined functions 88
4.6.1 Defining an analog function 88
4.6.2 Returning a value from an analog function 89
4.6.3 Calling an analog function 90

5 Signals . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
5.1 Analog signals 93
5.1.1 Access functions 93
5.1.2 Probes and sources 94
5.1.3 Examples 95
5.1.4 Port branches 97
5.1.5 Switch branches 98
5.1.6 Unassigned sources 99
5.2 Signal access for vector branches 99
5.2.1 Accessing net and branch signals 101
5.2.2 Accessing attributes 102
5.3 Contribution statements 102
5.3.1 Branch contribution statements 102
5.3.2 Indirect branch assignments 105

6 Analog behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
6.1 Analog procedural block 109
6.2 Block statements 110
6.2.1 Sequential blocks 110
6.2.2 Block names 111
6.3 Procedural assignments 111
6.4 Conditional statement 112
6.4.1 Examples 112
6.4.2 Analog conditional statements 113
6.5 Case statement 113
6.5.1 Analog case statements 114
6.5.2 Constant expression in case statement 115
6.6 Looping statements 115
6.6.1 Repeat and while statements 115
6.6.2 For statements 116
6.7 Events 117
6.7.1 Event detection 117
6.7.2 Event OR operator 118
6.7.3 Event triggered statements 119
6.7.4 Global events 119
6.7.5 Monitored events 121

7 Hierarchical structures. . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.1 Modules 125
7.1.1 Top-level modules 127
7.1.2 Module instantiation 127
7.2 Overriding module parameter values 130
7.2.1 Defparam statement 130
7.2.2 Module instance parameter value assignment by order 132
7.2.3 Module instance parameter value assignment by name 132
7.2.4 Parameter dependence 133
7.2.5 Detecting parameter overrides 133
7.2.6 Hierarchical system parameters 133
7.3 Paramsets 136
7.3.1 Paramset statements 137
7.3.2 Paramset overloading 139
7.3.3 Paramset output variables 140
7.4 Ports 141
7.4.1 Port association 141
7.4.2 Port declarations 142
7.4.3 Real valued ports 143
7.4.4 Connecting module ports by ordered list 144
7.4.5 Connecting module ports by name 144
7.4.6 Detecting port connections 145
7.4.7 Port connection rules 146
7.4.8 Inheriting port natures 146
7.5 Hierarchical names 146
7.6 Scope rules 148

8 Mixed signal . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
8.1 Introduction 149
8.2 Fundamentals 150
8.2.1 Domains 150
8.2.2 Contexts 150
8.2.3 Nets, nodes, ports, and signals 150
8.2.4 Mixed-signal and net disciplines 152
8.3 Behavioral interaction 152
8.3.1 Accessing discrete nets and variables from a continuous context 153
8.3.2 Accessing X and Z bits of a discrete net in a continuous context 154
8.3.3 Accessing continuous nets and variables from a discrete context 156
8.3.4 Detecting discrete events in a continuous context 157
8.3.5 Detecting continuous events in a discrete context 158
8.3.6 Concurrency 159
8.3.7 Function calls 160
8.4 Discipline resolution 160
8.4.1 Compatible discipline resolution 160
8.4.2 Connection of discrete-time disciplines 161
8.4.3 Connection of continuous-time disciplines 161
8.4.4 Resolution of mixed signals 162
8.5 Connect modules 165
8.6 Connect module descriptions 166
8.7 Connect specification statements 167
8.7.1 Connect module auto-insertion statement 168
8.7.2 Discipline resolution connect statement 170
8.7.3 Parameter passing attribute 171
8.7.4 connect_mode 171
8.8 Automatic insertion of connect modules 171
8.8.1 Connect module selection 173
8.8.2 Signal segmentation 175
8.8.3 connect_mode parameter 177
8.8.4 Rules for driver-receiver segregation and connect module selection and
insertion 181
8.8.5 Instance names for auto-inserted instances 182
8.9 Driver-receiver segregation 184
8.10 Driver access and net resolution 186
8.10.1 $driver_count 187
8.10.2 $driver_state 187
8.10.3 $driver_strength 187
8.10.4 driver_update 188
8.10.5 Receiver net resolution 188
8.10.6 Connect module example using driver access functions 189
8.11 Supplementary driver access functions 191
8.11.1 $driver_delay 191
8.11.2 $driver_next_state 191
8.11.3 $driver_next_strength 192
8.11.4 $driver_type 192

9 Scheduling semantics . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . 195
9.1 Introduction 195
9.2 Analog simulation cycle 195
9.2.1 Nodal analysis 195
9.2.2 Transient analysis 196
9.2.3 Convergence 197
9.3 Mixed-signal simulation cycle 198
9.3.1 Circuit initialization 199
9.3.2 Synchronization of analog and digital in transient analysis 199
9.3.3 The synchronization loop 204
9.3.4 Synchronization and communication algorithm 207
9.3.5 Assumptions about the analog and digital algorithms 208
9.4 Scheduling semantics for the digital engine 209
9.4.1 The stratified event queue 209
9.4.2 The Verilog-AMS digital engine reference model 210
9.4.3 Scheduling implication of assignments 211

10 System tasks and functions . . . . . . . .. .  . . . . . . . . . . . . . . . . . . . 215
10.1 Environment parameter functions 215
10.2 $random function 217
10.3 $dist_ functions 218
10.4 Simulation control system tasks 219
10.4.1 $finish 219
10.4.2 $stop 220
10.5 File operation tasks 220
10.5.1 $fopen 220
10.5.2 $fclose 221
10.6 Display tasks 221
10.6.1 Escape sequences for special characters 222
10.6.2 Format specifications 223
10.6.3 Hierarchical name format 223
10.6.4 String format 224
10.7 Announcing discontinuity 224
10.8 Time related functions 226
10.9 Limiting functions 226
10.10 Hierarchical system parameter functions 229
10.11 Hierarchy detection functions 230
10.12 Interpolation function 232
10.12.1 Table model inputs 233
10.12.2 Table data source 233
10.12.3 Extrapolation control string 234
10.12.4 Examples 235

11 Compiler directives . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .237
11.1 `default_discipline 237
11.2 `default_transition 238
11.3 `define and `undef 239
11.3.1 `define 239
11.3.2 `undef 241
11.4 `ifdef, `else, `endif 241
11.5 `include 242
11.6 `resetall 243
11.7 Predefined macros 244

12 Using VPI routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
12.1 The VPI interface 247
12.1.1 VPI callbacks 247
12.1.2 VPI access to Verilog-AMS HDL objects and simulation objects 248
12.1.3 Error handling 248
12.2 VPI object classifications 248
12.2.1 Accessing object relationships and properties 249
12.2.2 Delays and values 250
12.3 List of VPI routines by functional category 251
12.4 Key to object model diagrams 253
12.4.1 Diagram key for objects and classes 254
12.4.2 Diagram key for accessing properties 255
12.4.3 Diagram key for traversing relationships 256
12.5 Object data model diagrams 257
12.5.1 Module 258
12.5.2 Nature, discipline 259
12.5.3 Scope, task, function, IO declaration 260
12.5.4 Ports 261
12.5.5 Nodes 262
12.5.6 Branches 263
12.5.7 Quantities 264
12.5.8 Nets 265
12.5.9 Regs 266
12.5.10 Variables, named event 267
12.5.11 Memory 268
12.5.12 Parameter, specparam 269
12.5.13 Primitive, prim term 270
12.5.14 UDP 271
12.5.15 Module path, timing check, intermodule path 272
12.5.16 Task and function call 273
12.5.17 Continuous assignment 274
12.5.18 Simple expressions 275
12.5.19 Expressions 276
12.5.20 Contribs 277
12.5.21 Process, block, statement, event statement 278
12.5.22 Assignment, delay control, event control, repeat control 279
12.5.23 While, repeat, wait, for, forever 280
12.5.24 If, if-else, case 281
12.5.25 Assign statement, deassign, force, release, disable 282
12.5.26 Callback, time queue 283

13 VPI routine definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
13.1 vpi_chk_error() 287
13.2 vpi_compare_objects() 288
13.3 vpi_free_object() 289
13.4 vpi_get() 290
13.5 vpi_get_cb_info() 291
13.6 vpi_get_analog_delta() 292
13.7 vpi_get_analog_freq() 293
13.8 vpi_get_analog_time() 294
13.9 vpi_get_analog_value() 295
13.10 vpi_get_delays() 297
13.11 vpi_get_str() 300
13.12 vpi_get_analog_systf_info() 301
13.13 vpi_get_systf_info() 302
13.14 vpi_get_time() 303
13.15 vpi_get_value() 304
13.16 vpi_get_vlog_info() 310
13.17 vpi_get_real() 311
13.18 vpi_handle() 312
13.19 vpi_handle_by_index() 313
13.20 vpi_handle_by_name() 314
13.21 vpi_handle_multi() 315
13.21.1 Derivatives for analog system task/functions 315
13.21.2 Examples 315
13.22 vpi_iterate() 319
13.23 vpi_mcd_close() 321
13.24 vpi_mcd_name() 322
13.25 vpi_mcd_open() 323
13.26 vpi_mcd_printf() 324
13.27 vpi_printf() 325
13.28 vpi_put_delays() 326
13.29 vpi_put_value() 329
13.30 vpi_register_cb() 331
13.30.1 Simulation-event-related callbacks 332
13.30.2 Simulation-time-related callbacks 334
13.30.3 Simulator analog and related callbacks 335
13.30.4 Simulator action and feature related callbacks 335
13.31 vpi_register_analog_systf() 337
13.31.1 System task and function callbacks 338
13.31.2 Declaring derivatives for analog system task/functions 338
13.31.3 Examples 339
13.32 vpi_register_systf() 343
13.32.1 System task and function callbacks 343
13.32.2 Initializing VPI system task/function callbacks 345
13.33 vpi_remove_cb() 346
13.34 vpi_scan() 347
13.35 vpi_sim_control() 348

A Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
A.1 Source text 349
A.2 Natures 351
A.3 Disciplines 351
A.4 Declarations 352
A.5 Module instantiation 354
A.6 Mixed signal 354
A.7 Behavioral statements 355
A.8 Analog expressions 358
A.9 Expressions 358
A.10 General 361

B Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
B.1 All keywords 363
B.2 Discipline/nature 365
B.3 Connect rules 365

C Analog language subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
C.1 Verilog-AMS introduction 367
C.1.1 Verilog-A overview 367
C.1.2 Verilog-A language features 367
C.2 Lexical conventions 368
C.3 Data types 368
C.4 Expressions 369
C.5 Signals 369
C.6 Analog behavior 369
C.7 Hierarchical structures 369
C.8 Mixed signal 370
C.9 Scheduling semantics 370
C.10 System tasks and functions 370
C.11 Compiler directives 370
C.12 Using VPI routines 370
C.13 VPI routine definitions 370
C.14 Syntax 371
C.15 Keywords 371
C.16 Standard definitions 371
C.17 SPICE compatibility 371
C.18 Changes from previous Verilog-A LRM versions 372
C.19 Obsolete functionality 375
C.19.1 Forever 375
C.19.2 NULL 375
C.19.3 Generate 375

D Standard definitions . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 379
D.1 The disciplines.vams file 380
D.2 The constants.vams file 386
D.3 The driver_access.vams file 387

E SPICE compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
E.1 Introduction 389
E.1.1 Scope of compatibility 389
E.1.2 Degree of incompatibility 389
E.2 Accessing Spice objects from Verilog-AMS HDL 390
E.2.1 Case sensitivity 390
E.2.2 Examples 391
E.3 Preferred primitive, parameter, and port names 392
E.3.1 Independent sources 393
E.3.2 Unsupported components 394
E.3.3 Discipline of primitives 394
E.4 Limiting algorithms 395
E.5 Other issues 395
E.5.1 Multiplicity factor on subcircuits 396
E.5.2 Binning and libraries 396

F Discipline resolution methods . . .  . . . . . . . . . . . . . . . . . . . . . . . . 397
F.1 Discipline resolution 397
F.2 Resolution of mixed signals 397
F.2.1 Default discipline resolution algorithm 397
F.2.2 Alternate expanded analog discipline resolution algorithm 398

G Open issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

H Glossary . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 405

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