求哪位大侠帮忙写个testbench

yaqixinghuan · 发表于 2010-5-10 12:28:17

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我要用Verilog语言设计一个异步FIFO并用modelsim仿真出来，现在模块程序已经写好了，但是测试程序遇到问题了，请大侠们帮我写一个。下面我把我的各个模块程序附上。小女不胜感激
//verilog RTL for the read-clock domain to write-clock domain synchonizer module
module sync_r2w(wrptr2,rptr,wclk,wrst_n);
parameter ADDRSIZE=4;
output[ADDRSIZE:0]wrptr2;
input[ADDRSIZE:0]rptr;
input wclk,wrst_n;
reg[ADDRSIZE:0]wrptr2,wrptr1;
[email=always@(posedge]always@(posedge[/email] wclk or negedge wrst_n)
if (!wrst_n){wrptr2,wrptr1}<=0;
else {wrptr2,wrptr1}<={wrptr1,rptr};
endmodule

//verilog RTL for the write-clock domain to read-clock domain synchronizer module
module sync_w2r(rwptr2,wptr,rclk,rrst_n);
parameter ADDRSIZE=4;
output[ADDRSIZE:0]rwptr2;
input[ADDRSIZE:0]wptr;
input rclk,rrst_n;
reg[ADDRSIZE:0]rwptr2,rwptr1;
[email=always@(posedge]always@(posedge[/email] rclk or negedge rrst_n)
if (!rrst_n){rwptr2,rwptr1}<=0;
else {rwptr2,rwptr1}<={rwptr1,wptr};
endmodule

module rptr_empty(rempty,raddr,rptr,rwptr2,rinc,rclk,rrst_n);
parameter ADDRSIZE=4;
output rempty;
output [ADDRSIZE-1:0]raddr;
output [ADDRSIZE:0] rptr;
input [ADDRSIZE:0] rwptr2;
input rinc,rclk,rrst_n;
reg [ADDRSIZE:0]rptr,rbin,rgnext,rbnext;
reg raddrmsb,rempty;
//graystyle1 pointer
[email=always@(posedge]always@(posedge[/email] rclk or negedge rrst_n)
if (!rrst_n) begin
rptr<=0;
raddrmsb<=0;
end
else begin
rptr<=rgnext;
raddrmsb<=rgnext[ADDRSIZE]^rgnext[ADDRSIZE-1];
end
[email=always@(rptr]always@(rptr[/email] or rinc or rempty ) begin:Gray_inc
integer i;
for(i=0;i<=ADDRSIZE;i=i+1)
rbin=^(rptr>>i);//gray to binary converter
if(!rempty)
rbnext=rbin+rinc;//increment the fifo counter
else
rbnext=rbin;
rgnext=(rbnext>>1)^rbnext;//binary to gray converter
end
//memory read-address pointer
assign raddr={raddrmsb,rptr[ADDRSIZE-2:0]};
//generation empty flag
[email=always@(posedge]always@(posedge[/email] rclk or negedge rrst_n)
if(!rrst_n) rempty <=1'b1;
else rempty <=(rgnext==rwptr2);
endmodule

module wptr_full (wfull,waddr,wptr,wrptr2,winc,wclk,wrst_n);
parameter ADDRSIZE=4;
output wfull;
output[ADDRSIZE-1:0] waddr;
output [ADDRSIZE:0] wptr;
input [ADDRSIZE :0] wrptr2;
input winc,wclk,wrst_n;
reg [ADDRSIZE:0] wptr,wbin,wgnext,wbnext;
reg waddrmsb,wfull;
//graystyle1 pointer
[email=always@(posedge]always@(posedge[/email] wclk or negedge wrst_n)
if(!wrst_n) begin
wptr<=0;
waddrmsb<=0;
end
else begin
wptr<=wgnext;
waddrmsb<=wgnext[ADDRSIZE]^wgnext[ADDRSIZE-1];
end
[email=always@(wptr]always@(wptr[/email] or winc or wfull) begin:Gray_inc
integer i;
for(i=0;i<=ADDRSIZE;i=i+1)
wbin=^(wptr>>i);//gray to binary converter
if(!wfull)
wbnext=wbin+winc;//increment the fifo counter
else
wbnext=wbin;
wgnext=(wbnext>>1)^wbnext;//binary to grayconverter
end
//memory write-address pointer
assign waddr={waddrmsb,wptr[ADDRSIZE-2:0]};
//generation full flag
wire w_2ndmsb=wgnext[ADDRSIZE]^wgnext[ADDRSIZE-1];
wire wr_2ndmsb=wrptr2[ADDRSIZE]^wrptr2[ADDRSIZE-1];
always @(posedge wclk or negedge wrst_n)
if(!wrst_n) wfull<=1'b1;
else wfull<=((wgnext[ADDRSIZE]!==wrptr2[ADDRSIZE])&&(w_2ndmsb==wr_2ndmsb)&&(wgnext[ADDRSIZE-2:0]==wrptr2[ADDRSIZE-2:0]));
endmodule

//buffer memory arry
module fifomem(rdata,wdata,waddr,raddr,wclk,wclken);
parameter DATASIZE=8;//memory data word width
parameter ADDRSIZE=4;//number of memory address bits
output[DATASIZE-1:0]rdata;
input [DATASIZE-1:0]wdata;
input wclk,wclken;
input[ADDRSIZE-1:0]raddr,waddr;
//instantiation of a vendor's dual_PORT RAM
`ifdef VENDORRAM
VENOR_RAM MEM(.dout(rdata),.din(wdata),.waddr(waddr),.raddr(raddr),.wclken(wclken),.clk(clk));
`else
reg[DATASIZE-1:0] MEM[0:ADDRSIZE-1];
assign rdata=MEM[raddr];//output the data
always @(posedge wclk)
if(wclken) MEM[waddr]<=wdata;//store the data
`endif
endmodule

wycawyc · 发表于 2010-5-10 13:24:02

把你的bench发上来给大家看看。帮你参谋一下。

yaqixinghuan · 发表于 2010-5-10 22:24:20

2# wycawyc

`timescale 1ns/100ps
module testbench;
parameter DATASIZE=8;
reg[DATASIZE-1:0] wdata,rdata;
reg wclk,rclk,wrst_n,rrst_n;
reg winc,rinc;
wire wfull,rempty;
//
initial
begin
#2000 $finsh ;
end
//
afifo DUT (rdata,wdata,winc,rinc,rempty,wfull,wclk,rclk,wrst_n,rrst_n);
initial
begin
wclk=0;
rclk=0;
wrst_n=1;
rrst_n=1;
winc=0;
rinc=0;
wdata=0;
#10 wrst_n=0;rrst_n=0;
#10 wrst_n=1;rrst_n=1;
end
//
initial
begin
$fsdbDumpfile("verilog.fsdb");
$fsdbDumpvars(0,afifo);
end
//
initial
begin
$monitor($time,"rinc=%b,rempty=%b,wfull=%b,rdata=%b",rinc,rempty,wfull,rdata);
end
endmodule