K-DELTA-1-SIGMA MODULATORS FOR WIDEBAND ANALOG-TO-DIGITAL CONVERSION

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K-DELTA-1-SIGMA MODULATORS FOR WIDEBAND ANALOG-TO-DIGITAL CONVERSION

CONTENTS
Acknowledgements vi
Abstract viii
List of Tables xvi
List of Figures xxix
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Dissertation Organization . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Time-Interleaved Analog-to-Digital Converters 7
2.1 Time-Interleaved Analog-to-Digital Converters . . . . . . . . . . . . . 7
2.2 Non-uniformly Sampled Sinusoidal . . . . . . . . . . . . . . . . . . . 10
2.2.1 Path Offset Errors . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.2 Gain Mismatch Errors . . . . . . . . . . . . . . . . . . . . . . 13
2.2.3 Phase Skew Errors . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.4 Errors due to Bandwidth Mismatch . . . . . . . . . . . . . . . 18
2.3 Oversampling in Time-Interleaved ADCs . . . . . . . . . . . . . . . . 19
2.4 Randomization and Calibration . . . . . . . . . . . . . . . . . . . . . . 20
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 Wideband Analog-to-Digital Converters 21
3.1 Digital Calibration of ADCs . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Delta-Sigma Modulation . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1 First-order Delta-Sigma Modulator . . . . . . . . . . . . . . . 26
3.2.2 Second-order Delta-Sigma Modulator . . . . . . . . . . . . . . 28
3.3 Prior and Current Art in Wideband Delta-Sigma Modulators . . . . . . 31
3.3.1 Double-Sampling DSM . . . . . . . . . . . . . . . . . . . . . 31
3.3.2 Time-Interleaving of Delta-Sigma Modulators . . . . . . . . . . 37
3.3.3 Parallel Delta-Sigma Modulators . . . . . . . . . . . . . . . . 39
3.3.4 Wideband Continuous-Time Delta-Sigma Modulators . . . . . 44
3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4 The K-Delta-1-Sigma Modulator 49
4.1 Switched-Capacitor Integrator (SCI) Dynamics . . . . . . . . . . . . . 49
4.2 The K-Path Switched-Capacitor Integrator (K-SCI) . . . . . . . . . . . 53
4.2.1 Path Mismatch in the K-path SC Integrator . . . . . . . . . . . 61
4.3 The First-Order K-Delta-1-Sigma Modulator . . . . . . . . . . . . . . 62
4.3.1 Ideal Simulation Results . . . . . . . . . . . . . . . . . . . . . 65
4.3.2 Noise Flow in the KD1S Modulator . . . . . . . . . . . . . . . 66
4.4 Effects of Circuit Nonidealities in KD1S . . . . . . . . . . . . . . . . . 68
4.4.1 Finite Op-amp Unity-Gain Frequency ( fun) . . . . . . . . . . . 68
4.4.2 Finite Op-amp Gain . . . . . . . . . . . . . . . . . . . . . . . 72
4.4.3 Slewing in the Op-amp . . . . . . . . . . . . . . . . . . . . . . 74
4.4.4 Real Quantizer Effects . . . . . . . . . . . . . . . . . . . . . . 78
4.4.5 Capacitor Mismatch, Phase Skew and Noise Folding . . . . . . 87
4.4.6 Clock Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.5 Noise Effects in a KD1S Modulator . . . . . . . . . . . . . . . . . . . 95
4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5 A Second-Order KD1S Modulator Topology 109
5.1 A Second-Order KD1S Modulator . . . . . . . . . . . . . . . . . . . . 109
5.1.1 Integrator Saturation and Dynamic Range Scaling . . . . . . . . 114
5.1.2 Ideal Simulation Results . . . . . . . . . . . . . . . . . . . . . 116
5.2 Effects of the circuit non-idealities . . . . . . . . . . . . . . . . . . . . 118
5.2.1 Finite Op-amp Unity-Gain Frequency ( fun) . . . . . . . . . . . 118
5.2.2 Finite Op-amp Gain . . . . . . . . . . . . . . . . . . . . . . . 122
5.2.3 Real Quantizer Effects . . . . . . . . . . . . . . . . . . . . . . 123
5.2.4 Capacitor Mismatch and Clock Skew . . . . . . . . . . . . . . 131
5.2.5 Clock Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6 Synthesis of Higher-Order KD1S Modulators 135
6.1 Higher-order Delta-Sigma Modulators . . . . . . . . . . . . . . . . . . 135
6.1.1 Stability Considerations and Multi-Bit Modulators . . . . . . . 138
6.2 NTF Pole and Zero Optimization . . . . . . . . . . . . . . . . . . . . . 143
6.3 Loop-filter Architectures . . . . . . . . . . . . . . . . . . . . . . . . . 144
6.4 Synthesis procedure for KD1S modulators . . . . . . . . . . . . . . . . 148
6.4.1 The ABCD Matrix . . . . . . . . . . . . . . . . . . . . . . . . 149
6.4.2 K-path Integrator Modeling . . . . . . . . . . . . . . . . . . . 151
6.4.3 The State-Space Embedding Method . . . . . . . . . . . . . . . 155
6.4.4 Dynamic Range Scaling . . . . . . . . . . . . . . . . . . . . . 158
6.4.5 Mapping to a Loop-filter Architecture . . . . . . . . . . . . . . 159
6.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.5.1 A Second-order CIFB KD1S Modulator with NTF Zero Optimization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.5.2 A Third-order CIFF KD1S Modulator . . . . . . . . . . . . . . 163
6.6 Comparison with conventional DSMs . . . . . . . . . . . . . . . . . . 165
6.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
7 Chip Design and Testing 169
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
7.2 Delay-Locked Loop for Multi-phase Clock Generation . . . . . . . . . 169
7.2.1 Phase Frequency Detector (PFD) . . . . . . . . . . . . . . . . . 173
7.2.2 Charge Pump and Loop-Filter . . . . . . . . . . . . . . . . . . 176
7.2.3 Voltage-Controlled Delay-Line (VCDL) . . . . . . . . . . . . . 177
7.2.4 Non-overlapping clock generator . . . . . . . . . . . . . . . . . 178
7.2.5 DLL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 180
7.3 First-Order KD1S Modulator . . . . . . . . . . . . . . . . . . . . . . 181
7.3.1 KD1S Output Synchronization . . . . . . . . . . . . . . . . . . 182
7.4 Second-Order KD1S Modulator . . . . . . . . . . . . . . . . . . . . . 183
7.5 KD1S Modulator Circuit Blocks . . . . . . . . . . . . . . . . . . . . . 184
7.5.1 Switched-Capacitors . . . . . . . . . . . . . . . . . . . . . . . 184
7.5.2 Op-amps and Bias Generation Circuit . . . . . . . . . . . . . . 186
7.5.3 Comparators and Flip-Flop . . . . . . . . . . . . . . . . . . . . 191
7.6 Chip Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
7.7 Chip Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
7.7.1 First-order KD1S Modulator . . . . . . . . . . . . . . . . . . . 196
7.7.2 Second-order KD1S Modulator . . . . . . . . . . . . . . . . . 199
7.8 Test Setup and Procedure . . . . . . . . . . . . . . . . . . . . . . . . . 202
7.8.1 Test Board Design . . . . . . . . . . . . . . . . . . . . . . . . 203
7.9 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.9.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
7.10 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

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