ESD in layout

halu · 发表于 2008-7-21 09:37:51

感謝分享!!

phase2000 · 发表于 2008-7-21 10:44:28

thanks for your share

suk.qi · 发表于 2008-7-21 12:10:54

全文应该是：
Design and layout of a high ESD performance NPN structure forsubmicron BiCMOS/bipolar circuits
Chen, J.Z.; Xin Yi Zhang; Amerasekera, A.; Vrotsos, T.
Reliability Physics Symposium, 1996. 34th Annual Proceedings., IEEE International
Volume , Issue , 30 Apr-2 May 1996 Page(s):227 - 232
Digital Object Identifier 10.1109/RELPHY.1996.492124
Summary:This paper presents a high ESD performance NPN protection structure for advanced submicron BiCMOS and Bipolar processes. Using a Zener trigger circuit and a specific multi-emitter layout technique, this paper successfully demonstrates an optimal protection structure to meet the requirements imposed on advanced submicron circuit applications. The protection circuit has a low trigger voltage as well as a low capacitance load and does not add any series resistance

yuxi · 发表于 2008-9-21 11:34:46

ieee papaer

basildy · 发表于 2008-9-21 11:48:00

superricher · 发表于 2008-10-19 02:45:24

thank you

fanatic · 发表于 2008-10-21 18:26:57

rerere

pvtic · 发表于 2008-10-22 13:11:27

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seagull76 · 发表于 2008-10-22 14:22:30

thanks

zbplus · 发表于 2008-11-9 14:12:42

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ESD in layout

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