A 16b 65MSps Pipeline ADC Core with 230fs Clock Jitter

jason_zhuzhu · 发表于 2010-3-10 15:20:44

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abbr_e17da54d62e402834f59fd272055c2e9.pdf (341.73 KB , 下载次数: 199 )

oxplorer · 发表于 2010-3-10 17:44:16

see see

niulinux · 发表于 2010-3-10 19:50:37

这个不错，感谢楼主分享

langtaosha · 发表于 2010-3-14 15:46:40

感谢共享！！！！

cn12345678 · 发表于 2010-8-17 11:23:25

thanks

leonken460 · 发表于 2010-8-17 11:40:54

dddddddddddddddddd

xy85061182 · 发表于 2010-8-18 11:06:21

有效位是多少？

didibabawu · 发表于 2010-10-31 23:01:58

顶一记，正在找这个，呵呵

ztlin · 发表于 2011-1-25 11:19:09

回复 1# jason_zhuzhu
This work introduces key simulation techniques enabling
the design of a 16b 65MSps pipeline ADC in 0 . 4 ~ ~
45GHz-jr SiGe BiCMOS. A complete methodology for INL
investigation with SPICE leads to understand the distortion
introduced by Track/Hold as well as quantizer at 3.3V
supply and high input range (4Vpp). Simulations of aperture
uncertainty are presented that match the measured 230fs
jitter, yielding 74.5dBFS SNR at 150MHz input. The test
chip delivers 78.3dBFS SNR, 88dBc SFDR at
65MSpdlMHz with 97OmW power consumption.
Keywords: A-to-D and D/A conversion

xmuly · 发表于 2011-3-17 14:31:54

看下，希望有收获

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[资料] A 16b 65MSps Pipeline ADC Core with 230fs Clock Jitter

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