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The electronics industry has entered the era of multimillion-gate chips, and there’s no
turning back. By the year 2001, Sematech predicts that state-of-the-art ICs will
exceed 12 million gates and operate at speeds surpassing 600 MHz. An engineer
designing 100 gates/day would require a hypothetical 500 years to complete such a
design, at a cost of $75 million in today’s dollars. This will never happen, of course,
because the time is too long and the cost is too high. But 12-million gate ICs will hap-
pen, and soon.
How will we get there? Whatever variables the solution involves, one thing is clear:
the ability to leverage valuable intellectual property (IP) through design reuse will be
the invariable cornerstone of any effective attack on the productivity issue. Reusable
IP is essential to achieving the engineering quality and the timely completion of mul-
timillion-gate ICs. Without reuse, the electronics industry will simply not be able to keep pace with the challenge of delivering the “better, faster, cheaper” devices con-sumers expect.
Synopsys and Mentor Graphics have joined forces to help make IP reuse a reality. One of the goals of our Design Reuse Partnership is to develop, demonstrate, and doc-ument a reuse-based design methodology that works. The Reuse Methodology Man-ual (RMM) is the result of this effort. It combines the experience and resources of Synopsys and Mentor Graphics. Synopsys’ expertise in design reuse tools and Mentor Graphics’ expertise in IP creation and sourcing resulted in the creation of this manual that documents the industry’s first systematic reuse methodology. The RMM describes the design methodology that our teams have found works best for designing reusable blocks and for integrating reusable blocks into large chip designs.
It is our hope that this manual for advanced IC designers becomes the basis for an
industry-wide solution that accelerates the adoption of reuse and facilitates the rapid development of tomorrow’s large, complex ICs. |
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创芯大讲堂
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发表于 2010-3-8 11:46:50
