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【Responsibilities】
1. Manage a team of Logic design verification engineers to accomplish the task of verifying the functionality and performance of an HDL implementation with respect to the architectural and functional specification.
2. Work closely with ASIC/SOC design team to ensure functional and performance compliance with architectural and functional specification.
3. Must institute effective logic design verification methodology and documentation practice
4. Interface with OS/Driver software team to effectively use ASIC/SOC chip resources in software and re-use verification C/C++ code.
5. Interface with Physical design team for gate-level simulations and logic equivalency checks.
【Requirements】
1. MSEE or higher 5+ years experience in area of CMOS Logic design/verification and at least 2 years of project management.
2. Ability to implement effective verification flow and procedures for bus-based SOC’s and data-flow design blocks and sub-systems.
3. Must be knowledgeable to interface effectively with test development and OS/Driver software teams.
4. Must be familiar with ASIC/SOC design flow.
5. Knowledge of DTV and related products & functions a plus.
KT Human Resources Consulting Company (Shanghai) was established in 2001 in response to a need for a recruitment consultancy to be an active, contributing member of the semiconductor community, as opposed to simply a supplier to it.We provide professional search and talent acquisition in the Integrated Circuit、Electronic、Telecommunications industry of international corporations in Greater China. Our client list contains numerous international companies, many of them are long-term customers.
If you interested in the job, pls sent your cv to: hr@kthr.com, thanks! |
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