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【Responsibilities】
1. Manage a team of Logic design engineers to accomplish the task of transforming architecture/functional specification of chip to feasibility study and then silicon-worthy HDL format.
2. Interface with physical design to perform synthesis, STA, DFT and other physical design transformations and optimizations.
3. Interface with board design to implement reference boards.
4. Interface with OS/Driver software team to effectively use ASIC/SOC chip resources in software.
5. Work closely with ASIC/SOC verification team to ensure functional and performance compliance with architectural and functional specification.
【Requirements】
1. MSEE or higher 5+ years experience in area of CMOS Logic design and at least 2 years of project management.
2. Experience with 90nm or lower process based logic design and optimization.
3. Effective management of resources in ASIC/SOC Logic design cycles.
4. Knowledge of HDL, STA, Synthesis, DFT Tools a must.
KT Human Resources Consulting Company (Shanghai) was established in 2001 in response to a need for a recruitment consultancy to be an active, contributing member of the semiconductor community, as opposed to simply a supplier to it.We provide professional search and talent acquisition in the Integrated Circuit、Electronic、Telecommunications industry of international corporations in Greater China. Our client list contains numerous international companies, many of them are long-term customers.
If you interested in the job, pls sent your cv to: hr@kthr.com, thanks! |
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