Power Optimization in FPGA Designs

cxyfisher

IC designers today are facing continuous challenges in balancing design performance and power
consumption. This task is becoming more critical as designs grow larger and more complex and
process geometries shrink to 90-nm and below. FPGAs currently available provide performance
and features that designers want, but suffer due to higher power consumption requirements. This
growing need for maximizing performance while minimizing power consumption requires an
increasingly efficient power optimization without sacrificing performance.
The two primary sources of power consumption in FPGAs are:
• Dynamic power dissipation during charging and discharging of internal capacitances in
the logic array and interconnect networks of an active device
• Static power dissipation due to leaking currents during device standby
This paper will present power optimization techniques that reduce the dynamic power of the
design without affecting performance. Accurate toggle rate data information on each signal of
the design is most important when optimizing power requirements in the design. Using
simulation results is the most accurate way to generate signal activities representative of design
operating behavior. Also discussed will be VCS, an EDA simulator from Synopsys that assists in
obtaining accurate design toggle rates and utilizing this information to further optimize design
power, as well as an investigation of power estimation accuracy and the different components
used for good power estimation.

molf1998

回复 1# cxyfisher


   谢谢分享